Nanoscale CMOS circuit leakage power reduction By Double-gate device

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 102-107

  Kim, Keunwoo ^a   Das, Koushik K ^a   Joshi, Rajiv V ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Double gate device; Leakage power; Short channel effect

Indexed keywords

COMPUTER SIMULATION; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MONTE CARLO METHODS; MOSFET DEVICES; SEMICONDUCTOR DOPING;

CIRCUIT DESIGN; DOUBLE-GATE DEVICE; LEAKAGE POWER; SHORT-CHANNEL EFFECTS (SCE);

CMOS INTEGRATED CIRCUITS;

EID: 16244362046     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013267     Document Type: Conference Paper

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