Novel high-density low-power logic circuit techniques using DG devices

IEEE Transactions on Electron Devices

Volumn 52, Issue 10, 2005, Pages 2339-2342

  Chiang, Meng Hsueh ^a   Kim, Keunwoo ^b   Tretz, Christophe ^c   Chuang, Ching Te ^b  

^a NATIONAL ILAN UNIVERSITY   (Taiwan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM   (United States)

Author keywords

CMOS logic; Double gate (DG) MOSFETs

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); MOSFET DEVICES; NAND CIRCUITS;

DELAY EQUATIONS; LOGIC FUNCTIONS; NUMERICAL DEVICE SIMULATIONS;

LOGIC CIRCUITS;

EID: 33947158954     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.856191     Document Type: Article

References (8)

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