Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

Solid-State Electronics

Volumn 48, Issue 6, 2004, Pages 947-959

  Kranti, Abhinav ^a   Chung, Tsung Ming ^a   Flandre, Denis ^b   Raskin, Jean Pierre ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b Microelectronics Laboratory   (Belgium)

Author keywords

Device technology; Double gate MOSFET; Graded channel; Laterally asymmetric channel; Silicon on insulator

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DOPING (ADDITIVES); GATES (TRANSISTOR); MICROELECTROMECHANICAL DEVICES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

DEVICE TECHNOLOGY; DOUBLE GATE MOSFET; GRADED CHANNEL; LATERALLY ASYMMETRIC CHANNEL;

MOSFET DEVICES;

EID: 1442287310     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.12.014     Document Type: Article

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