Circuit performance of double-gate SOI CMOS

2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings

Volumn , Issue , 2003, Pages 266-267

  Lin, C H ^a   Su, P ^a   Taur, Y ^b   Xi, X ^a   He, I ^a   Niknejad, A M ^a   Chan, M ^c   Hu, C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; MOS DEVICES; SEMICONDUCTOR DEVICES; WORK FUNCTION;

CIRCUIT DESIGNS; CIRCUIT PERFORMANCE; DOUBLE-GATE MOSFETS; GATE OXIDE THICKNESS; LOAD CAPACITORS; PROPAGATION DELAYS; SHORT-CHANNEL EFFECT; WIRING CAPACITANCE;

MOSFET DEVICES;

EID: 84945281663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2003.1272091     Document Type: Conference Paper

References (7)

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7. Y. Taur, and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.