Two gates are better than one

IEEE Circuits and Devices Magazine

Volumn 19, Issue 1, 2003, Pages 48-62

  Solomon, P M ^a   Guarini, K W ^a   Zhang, Y ^a   Chan, K K ^a   Jones, E C ^a   Cohen, G M ^a   Krasnoperova, A ^b   Ronay, Maria ^a   Dokumaci, O ^b   Hovel, H J ^a   Bucchignano, J J ^a   Cabral Jr , C ^a   Lavoie, C ^a   Ku, V ^a   Boyd, D C ^b   Petrarca, K S ^b   Yoon, J H ^b   Babich, I V ^a   Treichler, J ^a   Kozlowski, P M ^a   Newbury, J S ^a   D'Emic, C P ^a   Sicina, R M ^a   Benedict, J ^b   Wong, H S P ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MATHEMATICAL MODELS; PERMITTIVITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

ELECTROSTATIC CONFINEMENT; INTERLEVEL DIELECTRICS; PHASE SHIFT MASK; TUNNELING CURRENTS;

MOSFET DEVICES;

EID: 0037235127     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2003.1175108     Document Type: Article

References (44)

1. R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. LeBlanc, "Design of ion implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, p. 256, 1974.
2. R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, in 2000 IEEE Int. Electron Devices Meeting, Tech. Dig., San Francisco, CA, p. 45.
3. H. Wakabayashi, M. Ueki, M. Narihiro, T. Fukai, N. Ikezawa, T. Matsuda, K. Yoshida, K. Takeuchi, Y. Ochiari, T. Mogami, and T. Kunio, in 2000 IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, p. 49.
4. B. Yu, H. Wang, A. Yoshi, Q Xiang, E. Ibok, and M-R. Lin, "15nm gate length planar CMOS transistor," 2001 IEEE Int. Electron Devices Meeting 2001 Tech. Dig., Washington, DC, p. 937.
5. D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and H-S.P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
6. D. Frank, S. Laux, and M. Fischetti, "Monte Carlo simulation of a 30nm dual-gate MOSFET: How far can Si go?" in 1992 IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, p. 553.
7. H.-S.P. Wong, D. Frank, P.M. Solomon, H.-J. Wann, and J. Welser, "Nanoscale CMOS," Proc. IEEE, vol. 87, pp. 537-570, Apr. 1999.
8. F. Assaderaghi, S. Park, D. Sinitsky, J. Bokor, P.-K. Ko, and C. Hu, "A dynamic threshold voltage MOSFET (DTMOS) for low voltage operation," IEEE Electron Device Lett., vol. 15, p. 510, 1994.
9. D. Frank, Y. Taur, and H.-S.P. Wong, "Generalized scale length for two-dimensional effects in MOS-FET's," IEEE Electron Device Lett., vol. 19, p. 385, 1998.
10. H.-S. Wong, D. Frank, and P. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," in 1998 IEEE Int. Electron Devices Tech. Dig, San Francisco, CA, p. 407.
11. D. Esseni, M. Mastrapasqua, G. Celler, F. Baumann, C. Fiegna, L. Selmi, and E. Sangiorgi, "Low field mobility of ultra-thin SOI n- and p- MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs," in 2000 IEEE Int. Electron Devices Meeting, San Francisco, CA, pp. 671-674.
12. M. Ieong, E. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. Roy, L. Shi, T. Furukawa, Y. Taur, R. Miller, and H.-S.P. Wong, "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs," in 2001 IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, 19-6, 19-6, p. 1.
13. J.M. Hergenrother, D. Monroe, F.P. Klemens, A. Komblit, G.R. Weber, W.M. Mansfield, R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A. Ciampa, R.A. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frankoviak, H.J. Gossmann, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleiman, W.Y.C. Lai, J.T. Lee, C.R.C. Liu, H.L. Maynard, M.D. Morris, S. Oh, H.C. Pai, S.C.S. Rafferty, J.M. Rosamilia, T.W. Sorsch, and H.H. Vuong, "The Vertical Replacement Gate (VRG) MOSFET: A 50-nm vertical MOSFET with lithography independent gate length," in 1999 IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, pp. 75.
14. J. Kedzierski, P. Xuan, E.H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin body MOSFETs for the 20 nm gate length regime," in 2000 IEEE Int. Electron Devices Meeting, Tech. Dig., San Francisco, CA, p. 57.
15. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA)-A novel vertical ultra thin SOI MOSFET," in 1989 IEEE Int. Electron Devices Meeting Tech Dig., Washington, DC, 1989, p. 833.
16. J. Kedzierski, D.M. Fried, E.J. Nowak, T. Kanarsky, J.H. Rankin, H. Hanfi, W. Natzle, D. Boyd, Y. Zhang, R.A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C.P. Willets, A. Johnson, S.P. Cole, H.E. Young, N. Carpenter, D. Rakowski, B.A. Rainey, P.E. Cottrell, M. Ieong, and H.-S.P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in 2001 IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, 19.5, p. 1
17. H-S. Wong, D.J. Frank, Y. Taur, and J.M.C. Stork, "Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs," in 1999 IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, p. 75.
18. T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, "Ultrafast low-power operation of p+ and n+ double-gate SOI MOSFETs," in 1994 Symp. VLSI Technol. Dig., Honululu, HI, p. 11.
19. E. Leobandung, J. Gu, L. Guo, and S. Chou, "Wire-channel and wrap-around-gate metal-oxide-semiconductor field-effect transistors with significant reduction in short-channel effects," J. Vac. Sci. Technol., vol. B-15, p. 2791, 1997.
20. H.-S. Wong, K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25nm thick silicon channel," in 1997 IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, p. 427.
21. G. Cohen, private communication.
22. T. Su, J.P. Denton, and G.W. Neudeck, "New planar self aligned double gate fully depleted P MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D)," in Proc. 2000 IEEE Int. SOI Conf., Wakefield, MA, p. 111.
23. T. Yoshimoto, M. Saito, T. Ohguro, M. Ono, H.S. Momose, and H. Iwai, "Silicided silicon-sidewall source and drain structure for high-performance 75-nm gate length pMOSFETs," in 1995 Symp. VLSI Technol. Dig., Kyoto, Japan, p. 11.
24. M. Bruel, B. Aspar, and A-J. Auberton-Herve, "Smart Cut: a new silicon on insulator material technology based on hydrogen implantation and wafer bonding," Jpn. J. Appl. Phys., vol. 36, pp. 1636-1641, 1997.
25. Q.-Y. Tong and U. Gösele, Semiconductor Wafer Bonding. New York: Wiley, 1999.
26. I. Yang, C. Vieri, A. Chandrakasan, and D. Antoniadis, "Back-gated CMOS on SOIAS for dynamic threshold voltage control," IEEE Trans. Electron Devices, vol. 44, p. 822, 1997.
27. Bonded SOI wafer purchased from SOITEC Inc., Peabody, MA.
28. G.M. Cohen, P.M. Mooney, E.C. Jones, K.K. Chan, P.M. Solomon, and H.-S.P. Wong, Appl. Phys. Lett., vol. 75, p. 787, 1999.
29. UV110 DUV photoresist purchased from Shipley Company, Marolborough, MA.
30. A. Krasnoperova, Y. Zhang, I. Babich, J. Treichler, J. Yoon, K. Guarini, and P. Solomon, "100 nm gate lithography for double gate transistors," XIV Conference on Optical Microlithography, Santa Clara, CA, 2001, Proc. SPIE, vol. 4346, p. 925, 2001.
31. J.M. Steigerwald, S.P. Murarka, and R.J. Gutman, Chemical Mechanical Planarization of Microelectronic Materials. New York: Wiley, 1997.
32. L. Peters, "Gaining control over STI processes," Semicond. Int., vol. 23, p. 71, 2000.
33. A.H. Liu, R. Solis, and J.H. Givens, "Utilization of optical metrology as an in line characterization technique for process performance improvement and yield enhancement of dielectric and metal CMP in IC manufacturing," Proc. SPIE, vol. 3743, p. 102, 1999.
34. T. Bibby and K. Holland, "Endpoint detection for CMP," J. Electron. Matter., vol. 27, no. 10, p. 1073, 1998.
35. A. Mathai and J. Schneir, "High resolution profilometry for improved overlay measurements of CMP processed layers," Proc. SPIE, vol. 3332, p. 182, 1998.
36. 4D) structure," in VLSI Symp. Tech. Dig., Kyoto, Japan, 1995, p. 11.
37. G.M. Cohen, C. Cabral, Jr., C. Lavoie, P.M. Solomon, K.W. Guarini, K.K. Chan, and R.A. Roy, "A self-aligned silicide process for thin silicon-on-insulator MOSFETs and bulk MOSFETs with shallow junctions," in Proc. 2001 MRS Fall Meeting, vol. 686.
38. Y. Taur, Y-J. Mii, R. Logan, H.-S. Wong, "On effective channel length in 0.1 μm MOSFETs," IEEE Electron Dev. Lett., vol. 16, p. 136, 1995.
39. R. Fletcher and M. Powell, "A rapidly convergent descent method for minimization," Comput. J., vol. 6, p. 163, 1963.
40. S. Villa, A.L. Lacaita, L.M. Perron, and R. Bez, "A physically-based model of the effective mobility in heavily-doped n-MOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 110-115, 1998.
41. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, 1994.
42. F.R. McFeely, K.K. Chan, E.C. Jones, P.M. Solomon, and J. Yurkas, "Method to protect refractory metal thin films requiring high temperature processing in oxidizing atmospheres," U.S. Patent 6,238,737,May 29, 2001.
43. L.J. Huang, K. Chan, P.M. Solomon, E. Jones, C. D'Emic, W.C. Lee, F.R. McFeely, and H.-S. Wong, "Preparation of 200mm silicon substrate with metal ground-plane for double-gate SOI devices," in Proc. 2000 IEEE SOI Int. Conf. Proc., Wakefield, MA, p. 14.
44. H. Shang, M. White, K. Guarini, P. Solomon, E. Cartier, F.R. McFeely, and J. Yurkas, "Tungsten gate MOS interface studies," Appl. Phys. Lett., vol. 78, p. 3139, 2001.