Planar double-gate SOI MOS devices: Fabrication by wafer bonding over pre-patterned cavities and electrical characterization

Solid-State Electronics

Volumn 51, Issue 2, 2007, Pages 231-238

  Chung, T M ^a   Olbrechts, B ^a   Sodervall U ^b   Bengtsson, S ^b   Flandre, D ^a   Raskin, J P ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

CMOS process; Planar double gate MOSFET; Silicon on insulator; Volume inversion; Wafer bonding

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC PROPERTIES; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

DOUBLE GATE (DG) MOS DEVICES; PLANAR DOUBLE GATE MOSFET; VOLUME INVERSION; WAFER BONDING;

MOS DEVICES;

EID: 33847311369     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.01.017     Document Type: Article

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