Nanoscale FinFETs with gate-source/drain underlap

IEEE Transactions on Electron Devices

Volumn 52, Issue 1, 2005, Pages 56-62

  Trivedi, Vishal ^a   Fossum, Jerry G ^a   Chowdhury, Murshed M ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

Effective channel length; FinFETs; Nanoscale CMOS devices; Source drain extensions; Underlap

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

DRAIN EXTENSIONS; FINFETS; NANOSCALE CMOS DEVICES; SOURCE EXTENSIONS;

FIELD EFFECT TRANSISTORS;

EID: 12344311284     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.841333     Document Type: Article

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