Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors

Solid-State Electronics

Volumn 49, Issue 6, 2005, Pages 1034-1043

  Lim, Tao Chuan ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Doping gradient; Double gate silicon on insulator (DGSOI); Fully depleted devices; Gate workfunction; MixedMode simulation spacer; Ultra thin silicon

Indexed keywords

CAPACITANCE; NANOSTRUCTURED MATERIALS; PARAMETER ESTIMATION; SENSITIVITY ANALYSIS; SILICON ON INSULATOR TECHNOLOGY; SPECIFICATIONS;

DOPING GRADIENT; DOUBLE GATE SILICON-ON-INSULATOR (DGSOI) TRANSISTORS; FULLY DEPLETED DEVICES; GATE WORKFUNCTION; MIXEDMODE SIMULATION SPACER; ULTRA-THIN SILICON;

GATES (TRANSISTOR);

EID: 18844432778     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.03.023     Document Type: Article

References (26)

1. International Technology Road Maps for Semiconductor 2003 edition. Available from http://public.itrs.net
2. T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horiguchi, and Y. Ono Ultimate thin double-gate SOI MOSFETs IEEE Trans Electron Dev 50 2003
3. Q. Chen, B. Agrawal, and J.D. Meindl A comprehensive analytical subthreshold swing (S) model for double gate devices IEEE Trans Electron Dev 49 2002 1086 1090
4. N.D. Jankovic, and G.A. Armstrong Performance comparison of double gate SOI MOSFETs on highly doped and near intrinsic layers Microelectron J 35 2004 647 654
5. B. Doris Device design considerations for ultra-thin SOI MOSFETs IEDM Tech Dig 2003 631 634
6. C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf Requirements for ultra-thin devices and new materials for the CMOS roadmap Solid-State Electron 48 2004 961 967
7. V.P. Trivedi, J.G. Fossum, and M.M. Chowdhury Nanoscale FinFETs with gate-source/drain underlap IEEE Trans Electron Dev 52 2005 56 62
8. J.G. Fossum, L.Q. Qang, J.W. Yang, S.H. Kim, and V.P. Trivedi Pragmatic design of nanoscale multi-gate CMOS IEDM Tech Dig 2004 613 616
9. M. Wong, and X. Shi On the threshold volatge of symmetrical DG MOS Capacitor with intrinsic silicon body IEEE Trans Electron Dev 51 2004 1600 1604
10. H. Shang, and M.H. White An ultra-thin midgap gate FDSOI MOSFET Solid-State Electron 44 2000 1621 1625
11. Q. Chen, E.M. Harell II, and J.D. Meindl A physical short-channel threshold voltage model for undoped symmetric double-gateMOSFETs IEEE Trans Electron Dev 50 July 2003 1631 1637
12. K. Kim, J.G. Fossum, and C.T. Chuang Process/physics-based threshold voltage for nano-scaled double gate devices Int J Electron 91 March 2004 139 148
13. J.G. Fossum, L. Ge, M.H. Chiang, V.P. Trivedi, M.M. Chowdhury, and L. Mathew A process/physics-based compact model for nonclassical CMOS device and circuit design Solid-State Electron 48 2004 919 926
14. ATLAS user's manual-device simulation software. SILVACO International Inc, 2004
15. B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, and J. Kavalieros High performance fully depleted tri-gate CMOS transistors IEEE Trans Electron Dev Lett 24 2003 263 265
16. D. Connelly, C. Faulkner, and D.E. Grupp Optimising Schottky S/D offset for 25 nm dual gate CMOS performance IEEE Trans Electron Dev Lett 24 June 2003 411 413
17. R. Granzner, V.M. Polyakov, F. Schwierz, M. Kittler, and T. Doll On the Suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs Solid-State Electron 19 2003 33 38
18. R.J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Städele, and W. Rösner Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime Solid-State Electron 47 2003 1199 1203
19. G.A. Kathawala, B. Winstead, and U. Ravaioli Monte Carlo simulations of double-gate MOSFETs IEEE Trans Electron Dev 50 2003 2467 2473
20. Y. Taur Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs IEEE Trans Electron Dev 48 2001 2861 2869
21. 2 CMOS transistors with high quality CVD TaN gate electrode IEEE Symposium on VLSI Circuits 2002 82 83
22. Y.V. Ponomarev, P.A. Stolk, C. Salm, J. Schmitz, and P.H. Woerlee High performance deep submicron CMOS technologies with polycrystalline-SiGe gates IEEE Trans Electron Dev 47 2000 848 855
23. + poly-SiGe gates. In Proceedings of 10th international symposium on integrated circuits, devices systems, ISIC, Singapore, 8-10 September 2004
24. T. Schulz, C. Pacha, R.J. Luyken, M. Stdele, J. Hartwich, and L. Dreeskornfeld Impact of technology parameters on device performance of UTB-SOI CMOS Solid-State Electron 48 2004 521 527
25. Y. Taur, and T.H. Ning Fundamentals of modern VLSI devices 1998 Cambridge University Press Cambridge
26. S. Xiong, and J. Bokor Sensitivity of double-gate and FinFET devices to process variations IEEE Trans Electron Dev 50 2003 2255 2261