Source/drain-doping engineering for optimal nanoscale FinFET design

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 192-194

  Trivedi, V P ^a   Fossum, J G ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC FIELDS; ELECTRIC POTENTIAL; GAUSSIAN NOISE (ELECTRONIC); MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTOR DOPING;

DOUBLE-GATE (DG) DEVICES; FIN-THICKNESS; SHORT CHANNEL EFFECTS (SCE); ULTRA-THIN SILICON BODY (UTB);

FIELD EFFECT TRANSISTORS;

EID: 13344249864     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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