Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics

Semiconductor Science and Technology

Volumn 21, Issue 12, 2006, Pages 1563-1572

  Kranti, Abhinav ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; GATES (TRANSISTOR); OPTIMIZATION; PERMITTIVITY;

DEVICE PARAMETERS; DOPING GRADIENTS; NANOSCALE SOURCE; SPACE WIDTHS;

MOSFET DEVICES;

EID: 33846859338     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/21/12/011     Document Type: Article

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