Low temperature (≤ 800°C) recessed junction selective silicon-germanium source/drain technology for sub-70 nm CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 437-440

  Gannavaram, S ^a   Pesovic, N ^a   Ozturk M C ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOW TEMPERATURE PROPERTIES; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

SOURCE/DRAIN TECHNOLOGY;

SEMICONDUCTING SILICON;

EID: 0034452629     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Shallow junction formation by low energy implant and high ramp-up rate RTA process
2. 25 nm CMOS design considerations
3. yfilms
4. +-n junctions for 35-70 nm CMOS using selectively deposited very heavily boron doped silicon-germanium films
5. An excimer-laser-based nanosecond thermal diffusion technique for ultra-shallow pn junction fabrication
6. 70 nm MOSFET with ultra-shallow, abrupt and super-doped S/D extension implemented by laser thermal process (LTP)