Digital circuit optimization via geometric programming

Operations Research

Volumn 53, Issue 6, 2005, Pages 899-932

  Boyd, Stephen P ^a   Kim, Seung Jean ^a   Patil, Dinesh D ^a   Horowitz, Mark A ^a  

^a Stanford University   (United States)

Author keywords

Digital circuit optimization; Engineering: computer aided design; Programming: geometric

Indexed keywords

DIGITAL CIRCUIT OPTIMIZATION; ENGINEERING: COMPUTER-AIDED DESIGN; PROGRAMING: GEOMETRIC;

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; DIGITAL CIRCUITS; MATHEMATICAL PROGRAMMING; PROBLEM SOLVING; ROBUSTNESS (CONTROL SYSTEMS);

OPTIMIZATION;

EID: 29244456551     PISSN: 0030364X     EISSN: 15265463     Source Type: Journal    
DOI: 10.1287/opre.1050.0254     Document Type: Article

References (149)

1. Abou-Seido, A., B. Nowak, C. Chu. 2004. Fitted Elmote delay: A simple and accurate interconnect delay model. IEEE Trans. VLSI Systems 12(7) 691-696.
2. Agarwal, A., V. Zolotov, D. Blaauw. 2003. Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 22(9) 1243-1260.
3. Alpert, C., A. Devgan, C. Kashyap. 2001a. RC delay metrics for performance optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 20(5) 571-582.
4. Alpert, C., A. Devgan, J. Fishburn, S. Quay. 2001b. Interconnect synthesis without wire tapering. Integration, the VLSI J. 20 90-114.
5. Alpert, C., C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. Quay. 2004. Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 23(1) 136-141.
6. Anis, M., M. Allam, M. Elmasry. 2002. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Trans. Very Large Scale Integration (VLSI) Systems 10(2) 71-78.
7. Anis, M., S. Areibi, M. Elmasry. 2003. Design and optimization of multi-threshold CMOS (MTCMOS) circuits. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems 22(10) 1324-1342.
8. Anklesaria, K., Z. Drezner. 1986. A multivariate approach to estimating the completion time for PERT networks. J. Oper. Res. Soc. 37 811-815.
9. Assaderaghi, F., D. Sinitsky, S. Parke, J. Bokor, P. Ko, C. Hu. 1997. Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI. IEEE Trans. Electron Devices 44(3) 414-422.
10. Augsburger, S., B. Nikolić. 2002a. Combining dual-supply, dual-threshold and transistor sizing for power reduction. Pwc. IEEE Internat. Conf. Comput. Design: VLSI in Computers and Processors. Cambridge, MA, 316-321.
11. Augsburger, S., B. Nikolić. 2002b. Reducing power with dual-supply, dual-thresholds and transistor sizing. Proc. IEEE Internat. Conf. Comput. Design: VLSI in Computers and Processors. Cambridge, MA, 16-18.
12. Bellaouar, A., A. Fridi, M. Elmasry, K. Itoh. 1998. Supply voltage scaling for temperature insensitive CMOS circuit operation. IEEE Trans. Circuits Systems II: Analog and Digital Signal Processing 45(3) 415-417.
13. Bharadwaj, B., M. Horowitz. 2000. Speed and power scaling of SRAMs. IEEE J. Solid-State Circuits 35(2) 175-185.
14. Bhardwaj, S., S. Vrudhula, D. Blaauw. 2003. TAU: Timing analysis under uncertainty. Internat. Conf. Comput.-Aided Design. San Jose, CA, 615-620.
15. Blaauw, D., V. Zolotov, S. Sundareswaran. 2002. Slope propagation in static timing analysis. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 21(10) 1180-1195.
16. Borah, M., R. Owens, M. Irwin. 1997. A fast algorithm for minimizing the Elmore delay to identified critical sinks. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 16(7) 753-759.
17. Bowman, R. 1995. Efficient estimation of arc criticalities in stochastic activity networks. Management Sci. 41(1) 58-67.
18. Bowman, K., L. Wang, X. Tang, J. Meindl. 2001. A circuit-level perspective of the optimum gate oxide thickness. IEEE Trans. Electron Devices 48(8) 1800-1810.
19. Boyd, S., L. Vandenberghe. 2004. Convex Optimization. Cambridge University Press, Cambridge, UK.
20. Boyd, S., S.-J. Kim, L. Vandenberghe, A. Hassibi. 2004. A tutorial on geometric programming. Optim. Engrg. Forthcoming. Available from www.stanford.edu/boyd/~gp_tutorial.html.
21. Brambilla, A., P. Maffezzoni. 2001. Statistical method for the analysis of interconnects delay in submicrometer layouts. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 20(8) 957-966.
22. Bryant, R., K.-T. Cheng, A. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey, A. Sangiovanni-Vincentelli. 2001. Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE 89(3) 341-365.
23. Calhoun, B., F. Honore, A. Chandrakasan. 2004. A leakage reduction methodology for distributed MTCMOS. IEEE J. Solid-State Circuits 39(5) 818-826.
24. Chabini, N., I. Chabini, E. Aboulhamid, Y. Savaria. 2003. Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 22(3) 346-351.
25. Chandrakasan, A., R. Brodersen. 1995. Minimizing power consumption in digital CMOS circuits. Proc. IEEE 83(4) 498-523.
26. Chang, J.-M., M. Pedram. 1997. Energy minimization using multiple supply voltages. IEEE Trans. Very Large Scale Integration Systems 5(4) 436-443.
27. Chen, C., M. Sarrafzadeh. 2002. Simultaneous voltage scaling and gate sizing for low-power design. IEEE Trans. Circuits Systems II: Analog and Digital Signal Processing 49(6) 400-408.
28. Chen, C., A. Srivastava, M. Sarrafzadeh. 2001. On gate level power optimization using dual-supply voltages. IEEE Trans. Very Large Scale Integration Systems 9(5) 616-629.
29. Chen, C.-P., D. Wong. 1999. Greedy wire-sizing is linear time. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 18(4) 398-405.
30. Chen, C.-R, C. Chu, D. Wong. 1999. Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems 18(7) 1014-1025.
31. Chen, K., H. Hu, P. Fang, M. Lin, D. Wollesen. 1997. Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects. IEEE Trans. Electron Devices 44(11) 1951-1957.
32. Chen, T.-C., S.-R. Pan, Y.-W. Chang. 2004. Timing modeling and optimization under the transmission line model. IEEE Trans. Very Large Scale Integration Systems 12(1) 28-41.
33. Chen, W., C.-T. Hseih, M. Pedram. 2000. Simultaneous gate sizing and placement. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 19(2) 206-214.
34. Chu, C., D. Wong. 1999. An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 18(9) 1297-1304.
35. Chu, C., D. Wong. 2001a. Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Automation of Electronic Systems 6(3) 343-371.
36. Chu, C., D. Wong. 2001b. VLSI circuit performance optimization by geometric programming. Ann. Oper. Res. 105 37-60.
37. Colleran, D., C. Portmann, A. Hassibi, C. Crusius, S. Mohan, S. Boyd, T. Lee, M. Hershenson. 2003. Optimization of phase-locked loop circuits via geometric programming. Proc. Custom Integrated Circuits Conf. (CICC). Orlando, FL, 326-328.
38. Cong, J., H. He. 1999. Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 18(4) 406-420.
39. Cong, J., L. He. 1996. Optimal wire sizing for interconnects with multiple sources. ACM Trans. Design Automation Electronic Systems 1(4) 478-511.
40. Cong, J., C.-K. Koh. 1994. Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integration Systems 2(4) 408-423.
41. Cong, J., K.-S. Leung. 1995. Optimal wiresizing under Elmore delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 14(3) 321-336.
42. Cong, J., Z. Pan. 2002. Wire width planning for interconnect performance optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 21(3) 319-329.
43. Cong, J., L. He, C.-K. Koh, P. Madden. 1996. Performance optimization of VLSI interconnect layout. Integration, the VLSI J. 21 1-94.
44. Davis, E. 1966. Resource allocation in project network models - A survey. J. Indust. Engrg. 17(4) 77-187.
45. Dawson, J., S. Boyd, M. Hershenson, T. Lee. 2001. Optimal allocation of local feedback in multistage amplifiers via geometric programming. IEEE Trans. Circuits Systems 148(1) 1-11.
46. Devroye, L. 1979. Inequalities for the completion times of stochastic PERT networks. Math. Oper. Res. 4(4) 441-447.
47. Dodin, B. 1984. Determining the K most critical paths in PERT networks. Oper. Res. 32 859-877.
48. Ebergen, J., J. Gainsley, P. Cunningham. 2004. Transistor sizing: How to control the speed and energy consumption of a circuit. Proc. 10th Internat. Sympos. Asynchronous Circuits Systems. Crete, Greece, 51-61.
49. Elmaghraby, S. 1970. Some Network Models in Management Science. Springer-Verlag, New York.
50. Elmaghraby, S. 1977. Project Planning and Control by Network Models. John Wiley and Sons, New York.
51. Elmore, W. 1948. The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19(1) 55-63.
52. Fishburn, J., A. Dunlop. 1985. TILOS: A posynomial programming approach to transistor sizing. IEEE Internat. Conf. Comput.-Aided Design: ICCAD-85. Digest Tech. Papers. IEEE Computer Society Press, Santa Clara, CA, 326-328.
53. Fishburn, J., C. Schevon. 1995. Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. 42(12) 1020-1022.
54. Gao, Y., D. Wong. 1999. Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 18(7) 994-999.
55. Gupta, R., B. Tutuianu, L. Pileggi. 1997. The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. Comput.-Aided Design of Integrated Circuits Systems 16(1) 95-104.
56. Hartley, H., A. Wortham. 1966. A statistical theory for PERT critical path analysis. Management Sci. 12(6) 469-481.
57. Hassibi, A., M. Hershenson. 2002. Automated optimal design of switchedcapacitor filters. Design, Automation and Test in Europe Conference and Exhibition. Paris, France, 1111.
58. Hershenson, M. 2002. Design of pipeline analog-to-digital converters via geometric programming. Proc. IEEE/ACM Internat. Conf. Comput. Aided Design. San Jose, CA, 317-324.
59. Hershenson, M. 2003. Analog design space exploration: Efficient description of the design space of analog circuits. Proc. 40th Design Automation Conf. Anaheim, CA, 970-973.
60. Hershenson, M., S. Boyd, T. Lee. 1998. GPCAD: A tool for CMOS op-amp synthesis. Pwc. IEEE/ACM Internat. Conf. Comput. Aided Design. San Jose, CA, 296-303.
61. Hershenson, M., A. Hajimiri, S. Mohan, S. Boyd, T. Lee. 1999. Design and optimization of LC oscillators. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design. San Jose, CA, 65-69.
62. Ho, R., K. Mai, M. Horowitz. 2001. The future of wires. Proc. IEEE 89(4) 490-504.
63. Hodges, D., H. Jackson, R. Saleh. 2004. Analysis and Design of Digital Integrated Circuits, 3rd ed. McGraw-Hill, New York.
64. Horowitz, M. 1984. Timing models for MOS circuits. Ph.D. thesis, Stanford University, Stanford, CA.
65. th assignment and device sizing with stack forcing. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED). Newport Beach, CA, 144-149.
66. Im, H., T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai. 2003. VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integration (VLSI) Systems 11(5) 755-761.
67. Ishihara, F., F. Sheikh, B. Nikolić. 2004. Level conversion for dual-supply systems. IEEE Trans. Very Large. Scale Integration (VLSI) Systems 12(2) 185-195.
68. Ismail, Y., E. Friedman, J. Neves. 2000. Equivalent Elmore delay for RLC trees. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 19(7) 83-97.
69. Jiang, I., Y. Chang, J. Jou. 2000. Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 19(9) 999-1010.
70. Johnson, M., D. Somasekhar, L.-Y. Chiou, K. Roy. 2002. Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integration (VLSI) Systems 10(1) 1-5.
71. Jung, S., K. Kim, S. Kang. 2003. Noise constrained power optimization for dual V, domino logic. IEEE Trans. Very Large Scale Integration (VLST) Systems 10(5) 532-541.
72. Jyu, H.-F., S. Malik, S. Devadas, K. Keutzer. 1993. Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Systems 1(2) 126-137.
73. Kahng, A., S. Muddu. 1997. An analytical delay model for RLC interconnects. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 16(12) 1507-1514.
74. Kao, I., M. Miyazaki, A. Chandrakasan. 2002. A 175mv multiplyaccumulate unit using an adaptive supply voltage and body bias architecture. IEEE J. Solid-State Circuits 37(11) 1545-1554.
75. Kao, J., A. Chandrakasan. 2000. Dual-threshold voltage techniques for low-power digital circuits. IEEE J. Solid-State Circuits 35(7) 1009-1018.
76. th allocation and device sizing in high performance microprocessors. Proc. 39th IEEE/ACM Design Automation Conf. New Orleans, LA, 486-491.
77. Kasamsetty, K., M. Ketkar, S. Sapatnekar. 2000. A new class of convex functions for delay modeling and its application to the transistor sizing problem. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 19(7) 779-788.
78. Kashyap, C., C. Alpert, F. Liu, A. Devgan. 2004. Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 23(4) 509-516.
79. Kay, R., L. Pileggi. 1998. EWA: Efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 17(1) 40-49.
80. Ketkar, M., S. Sapatnekar. 2002. Standby power optimization via transistor sizing and dual threshold voltage assignment. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design. San Jose, CA, 375-378.
81. th: Design and synthesis. IEEE Trans. Very Large Scale Integration (VLSI) Systems 11(1) 64-70.
82. Kim, K.-W., S.-O. Jung, P. Saxena, C. Liu, S. M. Kang. 2003b. Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integration (VLSI) Systems 11(5) 879-887.
83. Kim, S.J., S. Boyd, S. Yun, D. Patil, M. Horowitz. 2004. A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing. Submitted to Optim. Engrg. Available from www.stanford.edu/boyd/heur_san_opt.html.
84. Kleindorfer, G. 1971. Bounding distribution for stochastic acyclic networks. Oper. Res. 19 1586-1601.
85. Kong, J.-T. 2004. CAD for nanometer silicon design challenges and success. IEEE Trans. Very Large Scale Integration (VLSI) Systems 12(11) 1132-1147.
86. Krishnamurthy, R., L. Carley. 1997. Exploring the design space of mixed swing quadrail for low-power digital circuits. IEEE Trans. Very Large Scale Integration Systems 5(4) 389-400.
87. dd design. IEEE Trans. Very Large Scale Integration (VLSI) Systems 12(9) 926-936.
88. Lee, D., D. Blaauw, D. Sylvester. 2004. Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. Very Large Scale Integration Systems 12(2) 155-166.
89. Lee, Y.-M., C. Chen, D. Wong. 2002. Optimal wire-sizing function under the Elmore delay model with bounded wire sizes. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. 49(11) 1671-1677.
90. Lin, T., L. Pileggi. 2001. RC(L) interconnect sizing with second order considerations via posynomial programming. Proc. ACM/SIGDA Internat. Sympos. Physical Design. Sonoma, CA, 16-21.
91. Lindert, N., T. Sugii, S. Tang, C. Hu. 1999. Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages. IEEE J. Solid-State Circuits 34(1) 85-89.
92. th variation. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED). Newport Beach, CA, 2-7.
93. Lou, J., W. Chen, M. Pedram. 1999. Concurrent logic restructuring and placement for timing closure. Proc. IEEE/ACM Internat. Conf. Comput.-Aided Design. San Jose, CA, 31-35.
94. Lu, Y.-H., L. Benini, G. De Micheli. 2002. Dynamic frequency scaling with buffer insertion for mixed workloads. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 21(11) 1284-1305.
95. Ludwig, A., R. Möhring, F. Stork. 2001. A computational study on bounding the makespan distribution in stochastic project networks. Ann. Oper. Res. 102 49-64.
96. Mandal, P., V. Visvanathan. 2001. CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 20(1) 22-38.
97. Marković, D., V. Stojanović, B. Nikolić, M. Horowitz, R. Brodersen. 2004. Methods for true energy-performance optimization. IEEE J. Solid-State Circuits 39(8) 1282-1293.
98. Matson, M., L. Glasser. 1986. Macromodeling and optimization of digital MOS VLSI circuits. IEEE Trans. Comput.-Aided Design Integrated Circuits and Systems 5(4) 659-678.
99. Moh, T.-S., T.-S. Chang, S. Hakimi. 1996. Globally optimal floorplanning for a layout problem. IEEE Trans. Circuits Systems I: Fundamental Theory Appl. 43(29) 713-720.
100. Mohan, S., M. Hershenson, S. Boyd, T. Lee. 1999. Simple accurate expressions for planar spiral inductances. IEEE J. Solid-State Circuit 34(10) 1419-1424.
101. Mohan, S., M. Hershenson, S. Boyd, T. Lee. 2000. Bandwidth extension in CMOS with optimized on-chip inductors. IEEE J. Solid-State Circuits 35(3) 346-355.
102. Mukhopadhyay, S., C. Neau, R. Cakici, A. Agarwal, C. Kim, K. Roy. 2003. Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integration (VLSI) Systems 11(4) 716-730.
103. Nesterov, Y., A. Nemirovsky. 1994. Interior-Point Polynomial Methods in Convex Programming, Vol. 13. Studies in Applied Mathematics. SIAM, Philadelphia, PA.
104. Nguyen, D., A. Davare, D. Chinnery, B. Thompson, M. Orshansky, K. Keutzer. 2003. Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. Proc. Internat. Sympos. Low Power Electronics and Design (ISLPED), Seoul, Korea, 158-163.
105. Nocedal, J., S. J. Wright. 1999. Numerical Optimization. Springer Series in Operations Research. Springer, New York.
106. Orshansky, M., K. Keutzer. 2002. A general probabilistic framework for worst case timing analysis. Proc. 39th IEEE/ACM Design Automation Conf. New Orleans, LA, 556-561.
107. Orshansky, M., J. Chen, C. Hu. 1999. Direct sampling methodology for statistical analysis of scaled CMOS technologies. IEEE Trans. Semi-conductor Manufacturing 12(4) 403-408.
108. Pant, P., M. Roy, A. Chattejee. 2001. Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. IEEE Trans. Very Large Scale Integration Systems 9(2) 390-394.
109. Passy, U. 1998. Theory and algorithm of local refinement based optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 18(4) 406-420.
110. Patil, D., Y. Yun, S.-J. Kim, S. Boyd, M. Horowitz. 2005. A new method for robust design of digital circuits. Pwc. Internat. Sympos. Quality Electronic Design (ISQED). San Jose, CA, 676-681.
111. Pattanaik, M., S. Banerjee, B. Bahinipati. 2003. GP based transistor sizing for optimal design of nanoscale CMOS inverter. IEEE Conf. Nanotechnology. San Francisco, CA, 524-527.
112. Pedram, M. 1996. Power minimization in IC design: Principles and applications. ACM Trans. Design Automation of Electronic Systems 1(1) 3-56.
113. Pelgrom, M. 1989. Matching properties of MOS transistors. IEEE J. Solid State Circuits 24(5) 1433-1439.
114. Pillage, L., R. Rohrer. 1990. Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 9(4) 352-366.
115. Qin, Z., C.-K. Cheng. 2003. Realizable parasitic reduction using generalized Y-A transformation. Proc. 40th IEEE/ACM Design Automation Conf. Anaheim, CA, 220-225.
116. Rabaey, J., A. Chandrakasan, B. Nikolić. 2002. Digital Integrated Circuits: A Design Perspective, 2nd ed. Prentice-Hall, Englewood Cliffs, NJ.
117. Rezvani, P., M. Pedram. 2003. A fanout optimization algorithm based on the effort delay model. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 22(12) 1671-1678.
118. Robillard, P., M. Trahan. 1976. The completion times of PERT networks. Oper. Res. 25 15-29.
119. Roy, K., S. Mukhopadhyay, H. Mahmoodi-Meimand. 2003. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2) 305-327.
120. Rubenstein, J., P. Penfield, M. Horowitz. 1983. Signal delay in RC tree networks. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 2(3) 202-211.
121. Sakurai, T. 1988. Approximation of wiring delay in MOSFET LSI. IEEE J. Solid-State Circuits 18(4) 418-426.
122. Sakurai, T., A. Newton. 1990. Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25(2) 584-593.
123. Sancheti, P., S. Sapatnekar. 1996. Optimal design of macrocells for low power and high speed. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 15(9) 1160-1166.
124. Sapatnekar, S. 1996. Wire sizing as a convex optimization problem: Exploring the area-delay tradeoff. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 15 1001-1011.
125. Sapatnekar, S., W. Chuang. 2000. Power-delay optimization in gate sizing. ACM Trans. Design Automation of Electronic Systems 5(1) 98-114.
126. Sapatnekar, S., V. Rao, P. Vaidya, S. Kang. 1993. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput. -Aided Design Integrated Circuits Systems 12(11) 1621-1634.
127. Sathyamurthy, H., S. Sapatnekar, J. Fishburn. 1998. Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 17(2) 173-182.
128. Seidel, P., G. Even. 2004. Delay-optimized implementation of IEEE floating-point addition. IEEE Trans. Comput. 53(2) 97-113.
129. Shyu, J., A. Sangiovanni-Vincetelli, J. Fishburn, A. Dunlop. 1988. Optimization-based transistor sizing. IIEEE J. Solid-State Circuits 23(2) 400-409.
130. Singh, D., J. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, T. Mozdzen. 1995. Power conscious CAD tools and methodologies: A perspective. Proc. IEEE 83(4) 570-594.
131. th circuits. IEEE Trans. Very Large Scale Integration Systems 10(2) 79-90.
132. Sirisantana, N., K. Roy. 2004. Low-power design using multiple channel lengths and oxide thicknesses. IEEE Design Test Comput. 21(1) 56-63.
133. th assignment. IEEE Trans. Comput. -Aided Design Integrated Circuits Systems 23(5) 665-677.
134. Sutherland, I., B. Sproull, D. Harris. 1999. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, San Francisco, CA.
135. Sylvester, D., C. Hu. 2001. Analytical modeling and characterization of deep submicron interconnect. Proc. IEEE 89(5) 634-666.
136. Takahashi, O., S. Dhong, M. Ohkubo, S. Onishi, R. Dennard, R. Hannon, S. Crowder, S. Iyer, M. Wordeman, B. Davari, W. Weinberger, N. Aoki. 2000. IGHz fully pipelined 3.7ns address access time 8k 1024 embedded DRAM macro. ISSCC Digest of Tech. Papers. San Francisco, CA, 396-397.
137. Tschanz, J., S. Narendra, Y. Ye, B. Bloechel, S. Borkar, V. De. 2003. Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid-State Circuits 38(11) 1838-1845.
138. Usami, K., M. Horowitz. 1995. Clustered voltage scaling technique for low-power design. Proc. 1995 Internat. Sympos. Low Power Design. San Diego, CA, 3-8.
139. Van Slyke, R. 1963. Monte Carlo methods and the PERT problem. Oper. Res. 11 839-860.
140. Vanderhaegen, J., R. Brodersen. 2004. Automated design of operational transconductance amplifiers using reversed geometric programming. Proc. 41st IEEE/ACM Design Automation Conf. IEEE/ACM, San Diego, CA, 133-138.
141. Vittal, A., M. Marek-Sadowska. 1997. Low-power buffered clock tree design. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 16(9) 965-975.
142. Wei, L., Z. Chen, K. Roy, M. Johnson, Y. Ye, V. De. 1999. Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integration Systems 7(1) 16-24.
143. Weste, N., D. Harris. 2004. CMOS VLSI Design, 3rd ed. Addison Wesley, Boston, MA.
144. Xu, Y., L. Pileggi, S. Boyd. 2004. ORACLE: Optimization with recourse of analog circuits including layout extraction. Proc. 41st IEEE/ACM Design Automation Conf. IEEE/ACM, San Diego, CA, 151-154.
145. Yang, I., C. Vieri, A. Chandrakasan, D. Antoniadis. 1997. Back-gated CMOS on SOIAS for dynamic threshold voltage control. IEEE Trans. Electron Devices 44(5) 822-831.
146. Yang, N., W. Henson, J. Wortman. 2000. A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2100-nm gate oxides. IEEE Trans. Electronic Devices 47(8) 1636-1644.
147. Ye, Y. 1997. Interior Point Algorithms: Theory and Analysis. Wiley-Interscience Series in Discrete Mathematics and Optimization, Wiley, New York.
148. Yeh, Y.-J., S.-Y. Kuo, J.-Y. Jou. 2001. Converter-free multiple-voltage scaling techniques for low-power CMOS digital design. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 20(1) 172-176.
149. Young, F., C. Chu, W. Luk, Y. Wong. 2001. Handling soft modules in general nonslicing floorplan using Lagrangian relaxation. IEEE Trans. Comput.-Aided Design Integrated Circuits Systems 20(5) 687-692.