Fitted elmore delay: A simple and accurate interconnect delay model

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 7, 2004, Pages 691-696

  Abou Seido, Arif Ishaq ^a   Nowak, Brian ^b   Chu, Chris ^c  

^a INTEL CORPORATION   (United States)

^b IBM   (United States)

^c Iowa State University of Science and Technology   (United States)

Author keywords

Curve fitting technique; Delay model; Interconnect optimization; Physical design; Very large scale integration computer aided design (VLSI CAD)

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DATA REDUCTION; ELECTRIC SHIELDING; OPTIMIZATION; PARAMETER ESTIMATION;

CURVE FITTING TECHNIQUE; DELAY MODEL; INTERCONNECT OPTIMIZATION; VERY LARGE SCALE INTEGRATION COMPUTER-AIDED DESIGN (VLSI CAD);

VLSI CIRCUITS;

EID: 3142742282     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.830932     Document Type: Conference Paper

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