-
2
-
-
0022807522
-
An extension of Elmore delay
-
vol. CAS-33, no. 11, pp. 1147-1149, Nov. 1986.
-
P. K. Chan, "An extension of Elmore delay," IEEE Trans. Circ. Sys., vol. CAS-33, no. 11, pp. 1147-1149, Nov. 1986.
-
IEEE Trans. Circ. Sys.
-
-
Chan, P.K.1
-
4
-
-
0037710876
-
Charge-sharing models for switch-level simulation
-
vol. CAD-6, no. 6, pp. 1053-1060, 1987.
-
C. Chu and M. Horowitz, "Charge-sharing models for switch-level simulation," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 6, pp. 1053-1060, 1987.
-
IEEE Trans. Computer-Aided Design
-
-
Chu, C.1
Horowitz, M.2
-
6
-
-
0028576150
-
A gate-delay model for high-speed CMOS circuits
-
pp. 576-580.
-
F. Dartu, N. Menezes, J. Qian, and L. T. Pillage, "A gate-delay model for high-speed CMOS circuits," Proc. 31st Design Automation Conf., 1994, pp. 576-580.
-
Proc. 31st Design Automation Conf., 1994
-
-
Dartu, F.1
Menezes, N.2
Qian, J.3
Pillage, L.T.4
-
7
-
-
34748823693
-
The transient analysis of damped linear networks with particular regard to wideband amplifiers
-
vol. 19, no. 1, pp. 55-63, 1948.
-
W. C. Elmore, "The transient analysis of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, no. 1, pp. 55-63, 1948.
-
J. Appl. Phys.
-
-
Elmore, W.C.1
-
9
-
-
33747809906
-
Timing models for MOS circuits
-
M. A. Horowitz, "Timing models for MOS circuits," Ph.D. thesis, Stanford Univ., Stanford, CA, Jan. 1984.
-
Ph.D. Thesis, Stanford Univ., Stanford, CA, Jan. 1984.
-
-
Horowitz, M.A.1
-
10
-
-
0023386645
-
Timing analysis and performance improvement of MOS VLSI designs
-
vol. CAD-6, pp. 650-665, 1987.
-
N. P. Jouppi, "Timing analysis and performance improvement of MOS VLSI designs," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 650-665, 1987.
-
IEEE Trans. Computer-Aided Design
-
-
Jouppi, N.P.1
-
13
-
-
84985534659
-
The mean, median, mode inequality and skewness for a class of densities
-
vol. 23, no. 2, pp. 247-250, 1981.
-
H. L. MacGillivray, "The mean, median, mode inequality and skewness for a class of densities," Aust. J. Stat., vol. 23, no. 2, pp. 247-250, 1981.
-
Aust. J. Stat.
-
-
MacGillivray, H.L.1
-
16
-
-
0021120602
-
Switch-level delay models for digital MOS VLSI
-
"Switch-level delay models for digital MOS VLSI," Proc. 21st Des. Autom. Conf., 1984.
-
Proc. 21st Des. Autom. Conf., 1984.
-
-
-
20
-
-
84937077940
-
Theory of nonuniform RC lines, Part II: Analytic properties in the time domain
-
pp. 13-20, Mar. 1967.
-
E. N. Protonotarios and O. Wing, "Theory of nonuniform RC lines, Part II: Analytic properties in the time domain," IEEE Trans. Circuit Theory, pp. 13-20, Mar. 1967.
-
IEEE Trans. Circuit Theory
-
-
Protonotarios, E.N.1
Wing, O.2
-
21
-
-
85027171883
-
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
-
pp. 616-621.
-
R. Putatunda, "Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips," Proc. 19th Des. Autom. Conf., June 1981, pp. 616-621.
-
Proc. 19th Des. Autom. Conf., June 1981
-
-
Putatunda, R.1
-
22
-
-
0028444580
-
RICE: Rapid interconnect circuit evaluator using asymptotic waveform evaluation
-
pp. 763-776, June 1994.
-
C. Ratzlaff and L. T. Pillage, "RICE: Rapid interconnect circuit evaluator using asymptotic waveform evaluation," IEEE Trans. Computer-Aided Design, pp. 763-776, June 1994.
-
IEEE Trans. Computer-Aided Design
-
-
Ratzlaff, C.1
Pillage, L.T.2
-
23
-
-
0020778211
-
Signal delay in RC tree networks
-
vol. CAD-2, pp. 202-211, 1983.
-
J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, 1983.
-
IEEE Trans. Computer-Aided Design
-
-
Rubinstein, J.1
Penfield, P.2
Jr3
Horowitz, M.A.4
-
24
-
-
0042648626
-
Simulation tools for digital LSI design
-
C. J. Terman, "Simulation tools for digital LSI design," Ph.D. dissertation, Massachusetts Inst. Technol., Cambridge, MA, Sept. 1983.
-
Ph.D. Dissertation, Massachusetts Inst. Technol., Cambridge, MA, Sept. 1983.
-
-
Terman, C.J.1
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