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Volumn 49, Issue 11, 2002, Pages 1671-1677
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Optimal wire-sizing function under the Elmore delay model with bounded wire sizes
a a b |
Author keywords
Elmore delay; Optimal; Wire sizing
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Indexed keywords
ALGORITHMS;
BOUNDARY CONDITIONS;
CAPACITANCE;
COMPUTATIONAL COMPLEXITY;
COMPUTER SIMULATION;
DIFFERENTIAL EQUATIONS;
ELECTRIC RESISTANCE;
INTEGRAL EQUATIONS;
MATHEMATICAL MODELS;
OPTIMIZATION;
VLSI CIRCUITS;
BOUNDED WIRE SIZES;
ELMORE DELAY;
WIRE SIZING;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0036861749
PISSN: 10577122
EISSN: None
Source Type: Journal
DOI: 10.1109/TCSI.2002.804598 Document Type: Article |
Times cited : (14)
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References (8)
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