Speed and power scaling of SRAM's

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 2, 2000, Pages 175-185

  Amrutur, Bharadwaj S ^a,b   Horowitz, Mark A ^a  

^a Stanford University   (United States)

^b AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; INTERCONNECTION NETWORKS;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033895964     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.823443     Document Type: Article

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