-
1
-
-
0027594446
-
The impact of signal transition time on path delay computation
-
May
-
A. I. Kayssi, K. A. Sakallah, and T. N. Mudge, "The impact of signal transition time on path delay computation," IEEE Trans. Circuits and Systems, vol. 40, May 1993.
-
(1993)
IEEE Trans. Circuits and Systems
, vol.40
-
-
Kayssi, A.I.1
Sakallah, K.A.2
Mudge, T.N.3
-
2
-
-
0033351695
-
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
-
C. Visweswariah and A. R. Conn, "Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1999, pp. 244-251.
-
(1999)
Proc. IEEE/ACM Int. Conf. Computer-Aided Design
, pp. 244-251
-
-
Visweswariah, C.1
Conn, A.R.2
-
4
-
-
84989495069
-
Timing verification and the timing analysis program
-
R. B. Hitchcock, "Timing verification and the timing analysis program," in Proc. IEEE/ACM Design Automation Conf., 1982, pp. 594-604.
-
(1982)
Proc. IEEE/ACM Design Automation Conf.
, pp. 594-604
-
-
Hitchcock, R.B.1
-
7
-
-
0027840911
-
Computation of floating mode delay in combinational circuit: Theory and algorithms
-
Dec.
-
S. Devadas, K. Keutzer, and S. Malik, "Computation of floating mode delay in combinational circuit: Theory and algorithms," IEEE Trans. Computer-Aided Design, Dec. 1993.
-
(1993)
IEEE Trans. Computer-Aided Design
-
-
Devadas, S.1
Keutzer, K.2
Malik, S.3
-
8
-
-
0031359377
-
Approximate timing analysis of combinatorial circuits under XBD0 model
-
Y. Kukimoto, W. Gosti, A. Saldanha, and R. Brayton, "Approximate timing analysis of combinatorial circuits under XBD0 model," in IEEE Int. Conf. Computer-Aided Design, 1997, pp. 176-181
-
IEEE Int. Conf. Computer-Aided Design, 1997
, pp. 176-181
-
-
Kukimoto, Y.1
Gosti, W.2
Saldanha, A.3
Brayton, R.4
-
12
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
-
Apr.
-
T. Sakurai and A. R. Newton, "Alpha-Power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 584-594
-
-
Sakurai, T.1
Newton, A.R.2
-
14
-
-
0029344106
-
Methods to improve digital MOS macromodel accuracy
-
July
-
J. T. Kong and D. Overhauser, "Methods to improve digital MOS macromodel accuracy," IEEE Trans. Computer-Aided Design, vol. 14, pp. 868-881, July 1995.
-
(1995)
IEEE Trans. Computer-Aided Design
, vol.14
, pp. 868-881
-
-
Kong, J.T.1
Overhauser, D.2
-
15
-
-
0026106011
-
Delay analysis of series connected MOS-FETs
-
Feb.
-
T. Sakurai and A. R. Newton, "Delay analysis of series connected MOS-FETs," IEEE J. Solid-State Circuits, vol. 26. pp. 122-131, Feb. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 122-131
-
-
Sakurai, T.1
Newton, A.R.2
-
17
-
-
0024890438
-
Efficient algorithms for computing the longest viable path in a combinational network
-
P. C. McGeer and R. K. Brayton, "Efficient algorithms for computing the longest viable path in a combinational network," in Design Automation Conf., 1989, pp. 561-567.
-
Design Automation Conf., 1989
, pp. 561-567
-
-
McGeer, P.C.1
Brayton, R.K.2
-
18
-
-
0011543016
-
An approximate timing analysis of combinational circuits under XBD0 model
-
H. Yalcin, J. P. Hayes, and K. A. Sakallah, "An approximate timing analysis of combinational circuits under XBD0 model," in Int. Conf. Computer-Aided Design, 1997, pp. 176-181.
-
Int. Conf. Computer-Aided Design, 1997
, pp. 176-181
-
-
Yalcin, H.1
Hayes, J.P.2
Sakallah, K.A.3
-
21
-
-
0029717586
-
Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time
-
V. Chandramouli and K. A. Sakallah, "Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time," in Proc. Design Automation Conf., 1996.
-
Proc. Design Automation Conf., 1996
-
-
Chandramouli, V.1
Sakallah, K.A.2
-
22
-
-
0024737975
-
An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation
-
Y.-H. Jun, K. Jun, and S.-B. Park, "An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation," IEEE Trans. Computer-Aided Design, vol. 9, no. 6, pp. 1027-1032, 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.9
, Issue.6
, pp. 1027-1032
-
-
Jun, Y.-H.1
Jun, K.2
Park, S.-B.3
-
23
-
-
0028517487
-
Inverter models of CMOS gates for supply current and delay evaluation
-
A. Nabavi-Lishi and N. C. Rumin, "Inverter models of CMOS gates for supply current and delay evaluation," IEEE Trans. Computer-Aided Design, vol. 13, no. 10, pp. 1271-1279, 1994.
-
(1994)
IEEE Trans. Computer-Aided Design
, vol.13
, Issue.10
, pp. 1271-1279
-
-
Nabavi-Lishi, A.1
Rumin, N.C.2
-
24
-
-
0033725696
-
Removing user-specified false paths from timing graphs
-
D. Blaauw, R. Panda, and A. Das, "Removing user-specified false paths from timing graphs," in Proc. Design Automation Conf., 2000, pp. 270-273.
-
Proc. Design Automation Conf., 2000
, pp. 270-273
-
-
Blaauw, D.1
Panda, R.2
Das, A.3
-
25
-
-
0027701389
-
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
-
S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S.-M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Computer-Aided Design, vol. 12, no. 11, pp. 1621-1634.
-
IEEE Trans. Computer-Aided Design
, vol.12
, Issue.11
, pp. 1621-1634
-
-
Sapatnekar, S.S.1
Rao, V.B.2
Vaidya, P.M.3
Kang, S.-M.4
-
26
-
-
0031383851
-
TM microprocessor
-
TM microprocessor," in Proc. Int. Conf. Computer Design, 1997, pp. 143-148.
-
Proc. Int. Conf. Computer Design, 1997
, pp. 143-148
-
-
Dharchoudhury, A.1
Blaauw, D.2
Norton, J.3
Pullela, S.4
Dunning, J.5
-
28
-
-
0033320052
-
Crosstalk in VLSI interconnections
-
Dec.
-
A. Vittal, L. H. Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang, "Crosstalk in VLSI interconnections," Trans. on Computer-Aided Design, vol. 18, pp. 1817-1824, Dec. 1999.
-
(1999)
Trans. on Computer-Aided Design
, vol.18
, pp. 1817-1824
-
-
Vittal, A.1
Chen, L.H.2
Marek-Sadowska, M.3
Wang, K.-P.4
Yang, S.5
-
29
-
-
0033698637
-
On switching factor based analysis of coupled RC interconnects
-
A. B. Kahng, S. Muddu, and E. Sarto, "On switching factor based analysis of coupled RC interconnects," in Proc. IEEE/ACM Design Automation Conf., 2000, pp. 79-84.
-
Proc. IEEE/ACM Design Automation Conf., 2000
, pp. 79-84
-
-
Kahng, A.B.1
Muddu, S.2
Sarto, E.3
-
30
-
-
0032319737
-
Determination of worst-case aggressor alignment for delay calculation
-
P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of worst-case aggressor alignment for delay calculation," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1998, pp. 212-219.
-
Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1998
, pp. 212-219
-
-
Gross, P.D.1
Arunachalam, R.2
Rajagopal, K.3
Pileggi, L.T.4
-
33
-
-
0033685443
-
Clarinet: A noise analysis tool for deep submicron design
-
R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov, "Clarinet: A noise analysis tool for deep submicron design," in Proc. IEEE/ACM Design Automation Conf., June 2000, pp. 233-238.
-
Proc. IEEE/ACM Design Automation Conf., June 2000
, pp. 233-238
-
-
Levy, R.1
Blaauw, D.2
Braca, G.3
Dasgupta, A.4
Grinshpon, A.5
Oh, C.6
Orshav, B.7
Sirichotiyakul, S.8
Zolotov, V.9
-
34
-
-
0034841570
-
Driver modeling and alignment for worst-case delay noise
-
S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and J. Zuo, "Driver modeling and alignment for worst-case delay noise," in IEEE/ACM Design Automation Conf., 2001.
-
IEEE/ACM Design Automation Conf., 2001
-
-
Sirichotiyakul, S.1
Blaauw, D.2
Oh, C.3
Levy, R.4
Zolotov, V.5
Zuo, J.6
|