SpeEding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 2, 1998, Pages 173-182

  Sathyamurthy, Harsha ^a   Sapatnekar, Sachin S ^a   Fishburn, John P ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; OPTIMIZATION; SENSITIVITY ANALYSIS; SYNCHRONIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

ACYCLIC PIPELINE CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032000745     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.681267     Document Type: Article

References (19)

1. S. Malik, K. J. Singh, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Performance optimization of pipelined circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, 1990, pp. 410-413.
2. N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Resynthesis of multi-phase pipelines," in Proc. ACM/IEEE Design Autom. Conf., 1993, pp. 490-496.
3. J. Fishburn and A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. IEEE Int. Conf. Computer-Aided Design, 1985, pp. 326-328.
4. D. Marple and A. E. Gamal, "Optimal selection of transistor sizes in digital VLSI circuits," in Stanford Conf. VLSI, 1987, pp. 151-172.
5. J.-M. Shyu, A. L. Sangiovanni-Vincentelli, J. Fishburn, and A. Dunlop, "Optimization-based transistor sizing," IEEE]. Solid-State Circuits, vol. 23, pp. 400-409, Apr. 1988.
6. S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1621-1634, Nov. 1993.
7. M. A. B. Jackson, A. Srinivasan, and E. S. Kuh, "Clock routing for high-performance IC's," in Proc. ACM/IEEE Design Autom. Conf., 1990, pp. 573-579.
8. R.-S. Tsay, "An exact zero-skew clock routing algorithm," IEEE Trans. Computer-Aided Design, vol. 12, pp. 242-249, Feb. 1993.
9. J. P. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol. 39, pp. 945-951, July 1990.
10. R. B. Deokar and S. S. Sapatnekar, "A graph-theoretic approach to clock skew optimization," in Proc. IEEE Intl. Symp. Circuits Syst., 1994, pp. 1.407-1.410.
11. N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Minimum padding to satisfy short path constraints," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1993, pp. 156-161.
12. J. L. Neves and E. G. Friedman, "Circuit synthesis of clock distribution networks based on nonzero clock skew," in Proc. IEEE Int. Symp. Circuits Syst., 1994, pp. 4.175-4.178.
13. K. D. Wagner, "Clock system design," IEEE Design Test Comput., pp. 9-27, Oct. 1988.
14. M. Heshami and B. A. Wooley, "A 250-MHz skewed-clock pipelined data buffer," IEEE J. Solid-State Circuits, vol. 31, pp. 376-383, Mar. 1996.
15. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, "A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1993, pp. 220-223.
16. J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
17. P. E. Gill, W. Murray, and M. H. Wright, Numerical Linear Algebra and Optimization, vol. 1. Reading, MA: Addison-Wesley, 1991.
18. J. Ecker, "Geometric programming: Methods, computations and applications," SIAM Rev., vol. 22, pp. 338-362, July 1980.
19. 19 T. M. Burks, K. A. Sakallah, and T. N. Mudge, "Optimization of critical paths in circuits with level-sensitive latches," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 468-473.