Bandwidth extension in CMOS with optimized on-chip inductors

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 3, 2000, Pages 346-355

  Mohan, Sunderarajan S ^a,b   Del Mar Hershenson, Maria ^a,b   Boyd, Stephen P ^a   Lee, Thomas H ^a  

^a Stanford University   (United States)

^b Barcelona Design Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTATIONAL GEOMETRY; ELECTRIC CURRENTS; ELECTRIC INDUCTORS; GATES (TRANSISTOR); MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

GEOMETRIC PROGRAMMING; ON-CHIP INDUCTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0033872946     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.826816     Document Type: Article

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