Delay-Optimized Implementation of IEEE Floating-Point Addition

IEEE Transactions on Computers

Volumn 53, Issue 2, 2004, Pages 97-113

  Seidel, Peter Michael ^a   Even, Guy ^b  

^a Southern Methodist University   (United States)

^b TEL AVIV UNIVERSITY   (Israel)

Author keywords

Buffer insertion; Delay optimization; Dual path algorithm; Floating point addition; IEEE rounding; Logical effort; Optimized gate sizing

Indexed keywords

BUFFER INSERTION; DELAY OPTIMIZATION; DUAL PATH ALGORITHMS;

ADDERS; ALGORITHMS; APPROXIMATION THEORY; COMPUTER HARDWARE; GATES (TRANSISTOR); MATHEMATICAL MODELS; NUMBER THEORY; OPTIMIZATION; STANDARDS;

DIGITAL ARITHMETIC;

EID: 1342302647     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.1261822     Document Type: Article

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