Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses

IEEE Design and Test of Computers

Volumn 21, Issue 1, 2004, Pages 56-63

  Sirisantana, Naran ^a   Roy, Kaushik ^b  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS ESTIMATION; POWER CONSUMPTION; THRESHOLD CURRENTS;

ALGORITHMS; ASPECT RATIO; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; LEAKAGE CURRENTS; POWER ELECTRONICS; POWER INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; THICKNESS MEASUREMENT; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 1342281419     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.1261850     Document Type: Article

References (12)

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