메뉴 건너뛰기




Volumn 39, Issue 5, 2004, Pages 818-826

A leakage reduction methodology for distributed MTCMOS

Author keywords

Active leakage; Fine grain leakage reduction; Leakage reduction; MTCMOS; Sleep regions; Sneak leakage

Indexed keywords

COMBINATORIAL CIRCUITS; FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; POWER ELECTRONICS; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

EID: 2442466161     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.826335     Document Type: Article
Times cited : (94)

References (14)
  • 1
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • July-Aug.
    • S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, pp. 23-29, July-Aug. 1999.
    • (1999) IEEE Micro , vol.19 , pp. 23-29
    • Borkar, S.1
  • 2
    • 0031382110 scopus 로고    scopus 로고
    • Intrinsic leakage in low power deep submicron CMOS ICs
    • A. Keshavarzi et al., "Intrinsic leakage in low power deep submicron CMOS ICs," in Proc. Int. Test Conf., 1997, p. 146.
    • (1997) Proc. Int. Test Conf. , pp. 146
    • Keshavarzi, A.1
  • 3
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • Aug.
    • S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," J. Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
    • (1995) J. Solid-state Circuits , vol.30 , pp. 847-854
    • Mutoh, S.1
  • 4
    • 0033719725 scopus 로고    scopus 로고
    • Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration
    • T. Inukai et al., "Boosted Gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration," in Proc. IEEE Custom Integrated Circuits Conf., 2000, pp. 409-412.
    • (2000) Proc. IEEE Custom Integrated Circuits Conf. , pp. 409-412
    • Inukai, T.1
  • 5
    • 0031655481 scopus 로고    scopus 로고
    • A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current
    • H. Kawaguchi et al., "A CMOS scheme for 0.5 V supply voltage with pico-ampere standby current," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1998, pp. 192-193, 436.
    • (1998) IEEE Int. Solid-state Circuits Conf. Dig. Tech. Papers , pp. 192-193
    • Kawaguchi, H.1
  • 6
    • 0029542965 scopus 로고
    • A 1-V high-speed MTCMOS circuit scheme for power-down applications
    • S. Shigematsu et al., "A 1-V high-speed MTCMOS circuit scheme for power-down applications," in Symp. VLSI Circuits Dig. Tech. Papers, 1995, pp. 125-126.
    • (1995) Symp. VLSI Circuits Dig. Tech. Papers , pp. 125-126
    • Shigematsu, S.1
  • 7
    • 0033684884 scopus 로고    scopus 로고
    • Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: Smart series switch
    • P. van der Meer et al., "Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: smart series switch," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, 2000, pp. 1-4.
    • (2000) Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) , vol.4 , pp. 1-4
    • Van der Meer, P.1
  • 8
    • 0012109789 scopus 로고    scopus 로고
    • MTCMOS sequential circuits
    • J. Kao and A. Chandrakasan, "MTCMOS sequential circuits," in Proc. ESSCIRC, 2001, pp. 332-339.
    • (2001) Proc. ESSCIRC , pp. 332-339
    • Kao, J.1    Chandrakasan, A.2
  • 9
    • 0036957192 scopus 로고    scopus 로고
    • Automated selective multi-threshold design for ultra-low standby applications
    • K. Usami et al., "Automated selective multi-threshold design for ultra-low standby applications," in Proc. Int. Symp. Low-Power Electronics and Design (ISLPED), 2002, pp. 202-206.
    • (2002) Proc. Int. Symp. Low-power Electronics and Design (ISLPED) , pp. 202-206
    • Usami, K.1
  • 10
    • 0042134646 scopus 로고    scopus 로고
    • Architecting ASIC libraries and flows in nanometer era
    • C. Bittlestone et al., "Architecting ASIC libraries and flows in nanometer era," in Proc. Design Automation Conf., 2003, pp. 776-781.
    • (2003) Proc. Design Automation Conf. , pp. 776-781
    • Bittlestone, C.1
  • 11
    • 0031639695 scopus 로고    scopus 로고
    • MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
    • J. Kao et al., "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. Design Automation Conf, 1998, pp. 495-500.
    • (1998) Proc. Design Automation Conf , pp. 495-500
    • Kao, J.1
  • 14
    • 0038306265 scopus 로고    scopus 로고
    • Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: An alternative to clockgating scheme in leakage dominant era
    • K.-S. Min et al., "Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clockgating scheme in leakage dominant era," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 400-502.
    • (2003) IEEE Int. Solid-state Circuits Conf. Dig. Tech. Papers , pp. 400-502
    • Min, K.-S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.