Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 2, 2002, Pages 71-78

  Anis, Mohab H ^a,b   Allam, Mohamed W ^a,c   Elmasry, Mohamed I ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

^c PMC Sierra Ltd Burnaby   (Canada)

Author keywords

Digital complementary metal oxide semiconductor (CMOS); Dynamic logic circuit; High performance; Low power design; Performance tradeoffs

Indexed keywords

DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC; HIGH-SPEED DOMINO CIRCUIT; MULTITHRESHOLD CMOS SCHEME; SOFTWARE PACKAGE HSPICE;

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC GATES; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0036543296     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.994977     Document Type: Article

References (11)

1. CMOS technology-year 2010 and beyond
2. Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 μm logic designs
3. t MOSFET process and energy-delay measurement
4. Clock-delayed domino for dynamic circuit design
5. Design-performance trade-offs in CMOS-domino logic
6. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
7. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
8. 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
9. Dual threshold voltage domino logic
10. Performance of CMOS differential circuits