Low-power buffered clock tree design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 9, 1997, Pages 965-975

  Vittal, Ashok ^a   Marek Sadowska, Malgorzata ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

Author keywords

Clock distribution; Power estimation

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CORRELATION METHODS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PROBLEM SOLVING; TREES (MATHEMATICS);

CLOCK DISTRIBUTION; SOFTWARE PACKAGE HSPICE;

TIMING CIRCUITS;

EID: 0031223006     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.658565     Document Type: Article

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