1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 396-397

  Takahashi, O ^a   Dhong, S ^a   Ohkubo, M ^a   Onishi, S ^a   Dennard, R ^a   Hannon, R ^a   Crowder, S ^a   Iyer, S ^a   Wordeman, M ^a   Davari, B ^a   Weinberger, W B ^a   Aoki, N ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; DECODING; DYNAMIC RANDOM ACCESS STORAGE; FABRICATION; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS;

MACROS;

EID: 0034429685     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. High-performance 0.18μm embedded DRAM technology with copper BEOL
2. 2 16Bank 1Gb DDR SDRAM with hybrid bitline architecture