A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1545-1554

  Kao, James T ^a   Miyazaki, Masayuki ^a,b   Chandrakasan, Anantha P ^a  

^a Department of Civil and Environmental Engineering   (United States)

^b HITACHI LTD   (Japan)

Author keywords

Active power; Adaptive body biasing; Body biasing; Dynamic power; Dynamic voltage scaling; Low power; Subthreshold leakage; Triple well

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MATHEMATICAL MODELS; OPTIMIZATION;

ACTIVE POWER CONSUMPTION; ADAPTIVE BODY BIASING; DYNAMIC VOLTAGE SCALING; TRIPLE WELL TECHNOLOGY;

DIGITAL INTEGRATED CIRCUITS;

EID: 0036858382     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803957     Document Type: Article

References (20)

1. A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992.
2. A. Keshavarzi, K. Roy, and C. Hawkins, "Instrinsic leakage in low power deep submicron IC's," in Proc. Int. Test Conf., Nov. 1997, pp. 146-155.
3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
4. J. Kao and A. Chandrakasan, "Dual-threshold voltage techniques for low power digital circuits," IEEE J. Solid-State Circuits, vol. 35, pp. 1009-1018, July 2000.
5. t CMOS circuits for multiple on-chip power control," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 300-301.
6. t scheme," IEEE J. Solid-State Circuits, vol. 31, pp. 1770-1778, Nov. 1996.
7. Y. Ye, S. Borkar, and V. De, "A new technique for standby leakage reduction in high-performance circuits," in Proc. 1998 Symp. VLSI Circuits, June 1998, pp. 40-41.
8. M. Miyazaki, J. Kao, and A. Chandraksan, "A 175 mV multiply-accumulate unit using an Adaptive Supply Voltage and Body Bias (ASB) architecture," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 58-59.
9. J. Kao, "Subthreshold Leakage Control Techniques for Digital Circuits," Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, 2001.
10. V. Kaenel, M. Pardoen, E. Dijkstra, and E. Vittoz, "Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits," Proc. Int. Symp. Low-power Electronics and Design (ISLPED), pp. 78-79, 1994.
11. D. Liu and C. Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE J. Solid-State Circuits, vol. 28, pp. 10-17, Jan. 1993.
12. R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol. 32, pp. 1210-1216, Aug. 1997.
13. V. Gutnik and A. Chandrakasn, "An efficient controller for variable supply-voltage low power processing," in Proc. Symp. VLSI Circuits, June 1996, pp. 158-159.
14. J. Goodman, A. Dancy, and A. Chandrakasan, "An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1799-1809, Nov. 1998.
15. T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A dynamic voltage scaled microprocessor system," in Proc. ISSCC, Feb. 2000, pp. 294-295.
16. M. Miyazaki et al., "A 1.2-GIPS/W microprocessor using speed-adaptive theshold-voltage CMOS with forward bias," IEEE J. Solid-State Circuits, vol. 37, pp. 210-217, Feb. 2002.
17. ____, "A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS for low voltage LSI's," in Proc. Int. Symp. Low-Power Electronics and Design (ISLPED), 1998, pp. 49-53.
18. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 422-423.
19. t variation," in Proc. Int. Symp. Low-Power Electronics and Design (ISLPED), Aug. 1999, pp. 229-232.
20. I. Yang, C. Vieri, A. Chandraksan, and D. Antoniadis, "Back gated CMOS on SOIAS for dynamic threshold control," in Proc. IEDM, Dec. 1995, pp. 877-880.