Wire width planning for interconnect performance optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 3, 2002, Pages 319-329

  Cong, Jason ^a,b   Pan, Zhigang ^a,c  

^a IEEE   (United States)

^b Engineering IV   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Interconnect optimization; Wire planning; Wire sizing

Indexed keywords

COUPLING CAPACITANCE; OPTIMAL WIRE SIZING;

CAPACITANCE; COMPUTER AIDED DESIGN; COUPLED CIRCUITS; DELAY CIRCUITS; OPTIMIZATION; PERFORMANCE; SENSITIVITY ANALYSIS; SIZE DETERMINATION; SUPERCONDUCTING WIRE; VLSI CIRCUITS;

INTERCONNECTION NETWORKS;

EID: 0036494121     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.986425     Document Type: Article

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