A Fanout Optimization Algorithm Based on the Effort Delay Model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 12, 2003, Pages 1671-1678

  Rezvani, Peyman ^a   Pedram, Massoud ^a  

^a University of Southern California ^*  (United States)

Author keywords

Buffer insertion; Fanout optimization; Gate sizing; Logic design; Logical effort

Indexed keywords

BUFFER INSERTION; FANOUT OPTIMIZATION; GATE SIZING; LOGICAL EFFORT;

ALGORITHMS; BUFFER STORAGE; CAPACITANCE; ELECTRIC NETWORK TOPOLOGY; GATES (TRANSISTOR); OPTIMIZATION; PROBLEM SOLVING; TREES (MATHEMATICS);

LOGIC DESIGN;

EID: 0347316493     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.819423     Document Type: Article

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