Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 1, 2004, Pages 136-141

  Alpert, Charles ^a   Chu, Chris ^b   Gandham, Gopal ^a   Hrkic, Milos ^c   Hu, Jiang ^d   Kashyap, Chandramouli ^a   Quay, Stephen ^a  

^a IBM   (United States)

^b Iowa State University   (United States)

^c University of Illinois at Chicago   (United States)

^d TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Buffer insertion; Driver sizing; Interconnection optimization; Performance optimization

Indexed keywords

ACOUSTIC NOISE; ALGORITHMS; CAPACITANCE; COMPUTATIONAL METHODS; DELAY CIRCUITS; DYNAMIC PROGRAMMING; ELECTRIC LOADS; ENCAPSULATION; HEURISTIC METHODS; INTERPOLATION; OPTIMIZATION; TIMING CIRCUITS; TOPOLOGY; TREES (MATHEMATICS);

BUFFER INSERTION; DRIVER SIZING; INTERCONNECTION OPTIMIZATION; PERFORMANCE OPTIMIZATION;

BUFFER CIRCUITS;

EID: 0347761312     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.819910     Document Type: Article

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