Leakage control with efficient use of transistor stacks in single threshold CMOS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 1, 2002, Pages 1-5

  Johnson, Mark C ^a,b   Somasekhar, Dinesh ^a,c   Chiou, Lih Yih ^b   Roy, Kaushik ^a,b  

^a IEEE   (United States)

^b PURDUE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Complementary metal oxide semiconductor (CMOS) digital integrated circuits; Design automation; Leakage currents

Indexed keywords

DESIGN AUTOMATION; LEAKAGE CONTROL;

COMBINATORIAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; TRANSISTORS; VECTORS;

CMOS INTEGRATED CIRCUITS;

EID: 0036477154     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.988724     Document Type: Article

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