CAD for nanometer silicon design challenges and success

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 11, 2004, Pages 1132-1147

  Kong, Jeong Taek ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Computer aided design (CAD); Design for manufacturability (DFM); Leakage power; Nanometer; Noise; Power distribution; Process variability; Reliability; Resolution enhancement; Signal integrity; Technology CAD (TCAD)

Indexed keywords

CMOS INTEGRATED CIRCUITS; FLASH MEMORY; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROCESS ENGINEERING; RELIABILITY; SILICON; SPURIOUS SIGNAL NOISE;

DESIGN FOR MANUFACTURABILITY (DFM); LEAKAGE POWER; NANOMETER; POWER DISTRIBUTION; PROCESS VARIABILITY; RESOLUTION ENHANCEMENT; SIGNAL INTEGRITY; TECHNOLOGY CAD (TCAD);

COMPUTER AIDED DESIGN;

EID: 9244238140     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.836294     Document Type: Article

References (119)

1. G. Moore, "Cramming more components onto integrated circuits," Electron, vol. 38, pp. 114-117, 1965.
2. C.-G. Hwang, "Semiconductor memories for IT era," in IEEE Solid-State Circuits Conf., 2002, pp. 24-27.
3. _, "Nanotechnology enables a new memory growth model," Proc. IEEE, vol. 91, pp. 1765-1771, Nov. 2003.
4. R. W. Keyes, "Fundamental limits of silicon technology," Proc. IEEE, vol. 89, pp. 227-239, Mar. 2001.
5. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFET's and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
6. R. D. Isaac, "The future of CMOS technology," IBM J. Res. Develop., vol. 44, pp. 369-378, May 2000.
7. M. T. Bohr, "Nanotechnology goals and challenges for electronic applications," IEEE Trans. Nanotechnol., vol. 1, pp. 56-62, Mar. 2002.
8. A. L. Sangiovanni-Vincentelli, "The tides of EDA," in ACM/IEEE Design Automation Conf., 2003, p. xxvii.
9. A. B. Kahng, G. Nichols, B. Sheu, S. Borkar, J. Cohn, A. Domic, P. Groeneveld, L. Scheffer, and J.-P. Schoellkopf, "Panel-Nanometer design: Place your bets," in ACM/IEEE Design Automation Conf., 2003, pp. 546-547.
10. R. E. Bryant, K.-T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli, "Limitations and challenges of computer-aided design technology for CMOS VLSI," Proc. IEEE, vol. 89, pp. 341-365, Mar. 2001.
11. P. Magarshack and P. G. Paulin, "System-on-chip beyond the nanometer wall," in ACM/IEEE Design Automation Conf., 2003, pp. 419-424.
12. The International Technology Roadmap for Semiconductor, 2003 ed., Austin. TX. Design chapter.
13. C. H. Diaz, M.-C. Chang, T.-C. Ong, and J. Sun, "Process and circuit design interlock for application-dependent scaling tradeoffs and the optimization in the SoC era," IEEE J. Solid-State Circuits, vol. 38, pp. 444-449, Mar. 2003.
14. C. Bittlestone, A. Hill, V. Singhal, and N. V. Arvind, "Architecting ASIC libraries and flows in nanometer era," in ACM/IEEE Design Automation Conf., 2003, pp. 776-781.
15. C. Visweswariah, "Death, taxes, and failing chips," in ACM/IEEE Design Automation Conf., 2003, pp. 343-347.
16. K.-H. Lee, J.-K. Park, Y.-N. Yoon, D.-H. Jung, J.-P. Shin, Y.-K. Park, and J.-T. Kong. "Analyzing the effects of floating dummy-fills: From feature scale analysis to full-chip RC extraction," in IEDM Tech. Dig., 2001, pp. 685-688.
17. S.-Y. Oh, W.-Y. Jung, J.-T. Kong, and K.-H. Lee, "Interconnect modeling for VLSIs," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 1999, pp. 203-206.
18. S.-H. Lee, D.-Y. Lee, T.-J. Kwon, J.-H. Lee, Y.-K. Park, B.-S. Kim, and J.-T. Kong, "An efficient statistical model using electrical tests for GHz CMOS devices," in Int. Workshop Statistical Modeling, 2000, pp. 72-75.
19. S. G. Duvall, "A practical methodology for the statistical design of complex logic products for performance," IEEE Trans. VLSI Syst., vol. 3, pp. 112-123, Jan. 1995.
20. S.-H. Lee, C.-H. Choi, J.-T. Kong, J.-K. Park, C.-H. Choi, W.-S. Lee, and J.-H. Yoo, "An efficient statistical analysis methodology and its application to high-density DRAMs," in ACM/IEEE Int. Conf. Computer-Aided Design, 1997, pp. 459-464.
21. M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Computer-Aided Design, vol. 21, pp. 544-553, May 2002.
22. B. E. Stine, V. Mehrotra, D. S. Boning, J. E. Chung, and D. J. Ciplickas, "A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance," in IEDM Tech. Dig., 1997, pp. 133-136.
23. A. Wettstein, O. Penzin, E. Lyumkis, and W. Fichtner, "Random dopant fluctuation modeling with the impedance field method," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2003, pp. 91-94.
24. T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34 nm devices," in IEDM Tech. Dig., 2002, pp. 303-306.
25. M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, "Transistor matching in analog CMOS applications," in IEDM Tech. Dig., 1998, pp. 915-918.
26. A. Agarwal, V. Zolotov, and D. T. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE Trans. Computer-Aided Design, vol. 22, pp. 1243-1260, Sept. 2003.
27. S. Nassif, "Delay variability: Sources, impacts, and trends," in IEEE Solid-State Circuits Conf., 2000, pp. 368-369.
28. N. Cobb and A. Zakhor, "Experimental results on optical proximity correction and variable threshold model," in SPIE Int. Society Optical Engineering, vol. 3051, 1997, pp. 458-468.
29. J. F. Chen, T. Laiding, K. Wampler, and R. Caldwell, "Optical proximity correction for intermediate-pitch features using sub-resolution scattering bars," J. Vac. Sci. Technol. B, vol. 15, pp. 2426-2433, Nov. 1997.
30. A. Wong, R. Ferguson, S. Mansfield, A. Moless, D. Samuels, R. Schuster, and A. Tomas, "Level-specific lithography optimization for 1-Gb DRAM," IEEE Trans. Semiconduct. Manufact., vol. 13, pp. 76-87, Feb. 2000.
31. M. Kling, N. Cave, B. J. Falch, C. C. Fu, K. Green, K. Lucas, B. J. Roman, A. J. Reich, J. Sturtevant, R. Tian, D. Russell, L. Karklin, and Y. Wang, "Practicing extension of 248-nm DUV optical lithography using trim-mask PSM," in SPIE Int. Society Optical Engineering, vol. 3679, 1999, pp. 10-17.
32. H.-C. Kim, D.-S. Nam, C. Hwang, Y.-S. Kang, S.-G. Woo, H.-K. Cho, and W.-S. Han, "Level specific illumination optimization by Monte Carlo method," in SPIE Int. Society Optical Engineering, vol. 5040, 2003, pp. 244-17.
33. A. B. Kahng and Y. C. Pati, "Subwavelength optical lithography: Challenges and impact on physical design," in ACM Int. Symp. Physical Design, 1999, pp. 112-119.
34. L. W. Liebmann, S. M. Mansfield, A. K. Wong, M. A. Lavin, W. C. Leipold, and T. G. Dunham, "TCAD development for lithography resolution enhancement," IBM J. Res. Develop., vol. 45, no. 5, pp. 651-665, Sept. 2001.
35. D. C. Cole, E. Barouch, E. W. Conrad, and M. Yeung, "Using advanced simulation to aid microlithography development," Proc. IEEE, vol. 89, pp. 1194-1213, Aug. 2001.
36. S. Y. Zinn, S. H. Kim, S. W. Choi, and J. M. Sohn, "Fast topography simulation using differential method," in Proc. SPIE Int. Society Optical Engineering, vol. 5040, 2003, pp. 92-100.
37. W.-Y. Chung, T.-K. Kim, Y.-T. Kim, B.-J. Hwang, Y.-K. Park, and J.-T. Kong, "Photoresist flow simulation using the viscous flow model," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2003, pp. 43-46.
38. B.-C. Cha, Y.-H. Kim, S.-W. Choi, Y.-H. Yu, and J.-M. Sohn, "Evaluation of process capability for 50 keV with rectangular shaped beam using computer simulation," in Proc. 17th Annual BACUS Symp. Photomask Technology and Management, vol. 3236, Sept. 1997, pp. 34-41.
39. C.-H. Park, Y.-H. Kim, H.-J. Lee, J.-T. Kong, and S.-H. Lee, "Practical approach to control the full chip level gate CD in DUV lithography," in Proc. SPIE Int. Society Optical Engineering, vol. 3334, 1998, pp. 215-223.
40. J.-S. Park, C.-H. Park, S.-U. Rhie, Y.-H. Kim, M.-H. Yoo, J.-T. Kong, H.-W. Kim, and S.-I. Yoo, "An efficient rule-based OPC approach using a DRC tool for 0.18 μm ASIC," in Int. Symp. Quality Electronic Design, 2000, pp. 82-86.
41. J.-S. Park, D.-H. Kim, H.-W. Kim, C.-H. Park, Y.-H. Kim. M.-H. Yoo, and J.-T. Kong, "Robust and fast metal OPC approach for 0.13 μm logic devices," in SPIE Int. Society Optical Engineering, vol. 4562, 2001, pp. 1104-1111.
42. C.-H. Park, S.-U. Rhie, J.-H. Choi, H.-W. Seo, Y.-H. Kim, Y.-K. Park, W.-S. Han, W.-S. Lee, and J.-T. Kong, "Optical proximity correction considering mask manufacturability and its application to 0.25 μm DRAM for enhanced device performance," in SPIE Int. Society Optical Engineering, vol. 4000, 2000, pp. 1041-1046.
43. W.-Y. Chung, T.-K. Kim, K.-I. Seo, Y.-K. Park, and J.-T. Kong, "Profile and equipment simulation for the self-aligned contact etch process by C4F8 plasmas," in Dry Process Symp., 2001, pp. 291-295.
44. C.-H. Park, S.-H. Choi, S.-U. Rhie, D.-H. Kim, J.-S. Park, T.-H. Jang, J.-S. Park, Y.-H. Kim, M.-H. Yoo, and J.-T. Kong, "Hybrid PPC method based on the empirical etch model for the 0.14 μm DRAM generation and beyond," in Int. Symp. Quality Electronic Design, 2002, pp. 143-148.
45. S.-H. Choi, J.-S. Park, C.-H. Park, W.-Y. Chung, I.-S. Kim, D.-H. Kim, Y.-H. Kim, M.-H. Yoo, and J.-T. Kong, "Hybrid PPC methodology using multi-step correction and implementation for the sub-100 nm node," in SPIE Int. Society Optical Engineering, vol. 5040, 2003, pp. 1176-1183.
46. S. D. Shang, Y. Granik, N. B. Cobb, W. Maurer, Y. Cui, L. W. Liebmann, J. M. Oberschmidt, R. Singh, and B. Vampatella, "Failure prediction across process window for robust OPC," in SPIE Int. Society Optical Engineering, vol. 5040, 2003, pp. 431-440.
47. S.-H. Choi, Y.-C. Ban, D.-H. Kim, J.-S. Hong, C.-H. Park, Y.-H. Kim, M.-H. Yoo, and J.-T. Kong, Simulation-based critical area extraction and litho-friendly layout design for the low k1 process, in SPIE Int. Society Optical Engineering, vol. 5377, pp. 713-720, 2004.
48. G. Nanz and L. E. Camilletti, "Modeling of chemical-mechanical polishing: A review," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 382-389, Nov. 1995.
49. Y.-H. Kim, T.-K. Kim, H.-J. Lee, J.-T. Kong, and S.-H. Lee, "CMP profile simulation using an elastic model based on nonlinear contact analysis," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 1997, pp. 69-72.
50. H. Takahashi, K. Tokunaga, T. Kasuga, and T. Suzuki, "Modeling of chemical-mechanical polishing process for three-dimensional simulation," in VLSI Technology Symp. Tech. Dig., 1997, pp. 25-26.
51. Y.-H. Kim, K.-J. Yoo, K.-H. Kim, B.-Y. Yoon, Y.-K. Park, S.-R. Hah, and J.-T. Kong, "CHAMPS (CHemicAl mechanical planarization simulator)," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2000, pp. 123-126.
52. K.-H. Kim, Y.-H. Kim, K.-B. Kim, C.-K. Hong, M.-H. Yoo, J.-L. Nam, J.-T. Kong, and S.-I. Lee, "A study on STI and damascene CMP using chip level simulation," Proc. Materials Research Society, vol. 671, p. M4.7, 2001.
53. F. G. Shi, B. Zhao, and S.-Q. Wang, "A new theory for CMP with soft pads," in Int. Interconnect Tech. Conf., 1998, pp. 73-75.
54. B. Zhao and F. G. Shi, "Threshold pressure and its influence in chemical mechanical polishing for IC fabrication," in Proc. Int. Electron Devices Meeting Tech. Dig., 1998, pp. 12.7.1-12.7.4.
55. D. White, J. Melvin, and D. Boning, "Characterization and modeling of dynamic thermal behavior in chemical mechanical polishing (CMP)," J. Electrochemical Society, vol. 150, pp. G271-G278, Apr. 2003.
56. B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor, "The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes," IEEE Trans. Electron Devices, vol. 45, pp. 665-679, Mar. 1998.
57. A. B. Kahng, G. Robins, A. Singh, and A. Zelikovsky, "Filling algorithms and analyzes for layout density control," IEEE Trans. Computer-Aided Design, vol. 18, pp. 445-462, Apr. 1999.
58. J.-K. Park, K.-H. Lee, J.-H. Lee, Y.-K. Park, and J.-T. Kong, "An exhaustive method for characterizing the interconnect capacitance considering floating dummy-fills by employing an efficient field solving algorithm," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2000, pp. 98-101.
59. W.-S. Lee, K.-H. Lee, J.-K. Park, T.-K. Kim, Y.-K. Park, and J.-T. Kong, "Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry," in Int. Symp. Quality Electronic Design, 2003, pp. 373-376.
60. Y. Chen, P. Gupta, and A. B. Kahng, "Performance-impact limited area fill synthesis," in IEEE Design Automation Conf., 2003, pp. 22-27.
61. W. K. Preston Jr., R. N. Athay, and W. J. Trybula, "Applying DFM in the semiconductor industry," in Electronics Manufacturing Technology Symp., 1995, pp. 438-441.
62. W. Maly, H. Heineken, J. Khare, and P. K. Nag, "Design for manufacturability in submicron domain," in IEEE Int. Conf. Computer-Aided Design, 1996, pp. 690-697.
63. T. G. Waring, G. A. Allan, and A. I. Walton, "Integration of DFM techniques and design automation," in IEEE Int. Symp. Defect Fault Tolerance VLSI Systems, 1996, pp. 59-67.
64. K. Veelenturf, "The road to better reliability and yield embedded DfM tools," in Design, Automation, Test Europe Conf. Exhibition, 2000, pp. 67-68.
65. N. Harrison, "A simple via duplication tool for yield enhancement," IEEE Int. Symp. Defect Fault Tolerance VLSI Systems, pp. 39-47, 2001.
66. A. B. Kahng, B. Liu, and I.I. Mandoiu, "Non-tree routing for reliability and yield improvement," in IEEE Int. Conf. Computer-Aided Design, 2002, pp. 260-266.
67. C. W. Strolenberg, "Stay away from minimum design-rule values [DFM in ultra-deep submicron processes]," in Design, Automation, Test Europe Conf. Exhibition, 2000, pp. 71-72.
68. C. Ouyang, H. T. Heineken, J. Khare, S. Shaikh, and M. d'Abreu, "Maximizing wafer productivity through layout optimizations," in 13th Int. Conf. VLSI Design, 2000, pp. 192-197.
69. S. V. Kosonocky, A. J. Bhavnagarwala, K. Chin, G. D. Gristede, A. M. Haen, W. Hwang, M. B. Kelchen, S. Kim, D. R. Knebel, K. W. Warren, and V. Zyuban, "Low-power circuits and technology for wireless digital systems," IBM J. Res. Develop., vol. 47, pp. 283-298, Mar./May 2003.
70. W. Kwon and T. Kim, "Optimal voltage allocation techniques for dynamically variable voltage processors," in IEEE Design Automation Conf., 2003, pp. 125-130.
71. L. Benini and G. De Micheli, "System-level power optimization: Techniques and tools," in ACM Trans. Design Automation Electronic Systems, vol. 5, Apr. 2000, pp. 115-192.
72. S. Gupta and F. N. Najm, "Energy and peak-current per-cycle estimation at RTL," IEEE Trans. VLSI Syst., vol. 11, pp. 525-537, Aug. 2003.
73. S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," in Int. Symp. Low-Power Electronics Design, 2003, pp. 172-175.
74. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling," in IEEE Design Automation Conf., 2003, pp. 169-174.
75. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," in Int. Symp. Low-Power Electronics Design, 2003, pp. 84-89.
76. G. Pei, W. Ni, A. V. Kammula, B. A. Minch, and E. C. Kan, "A physical compact model of DG MOSFET for mixed-signal circuit applications - Part I: Model description," IEEE Trans. Electron Devices, vol. 50, pp. 2135-2143, Oct. 2003.
77. R. Kumar and C. P. Ravikumar, "Leakage power estimation for deep sub-micron circuits in an ASIC design environment," in Int. Conf. VLSI Design, 2002, pp. 45-50.
78. T. Ishihara and K. Asada, "A system level memory power optimization technique using multiple power supply and threshold voltages," in IEEE Asia-South Pacific Design Automation Conf., 2001, pp. 456-461.
79. H.-S. Won, K.-S. Kim, K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong, "An MTCMOS design methodology and its application to mobile computing," in Int. Symp. Low-Power Electronics Design, 2003, pp. 110-115.
80. T. Kuroda, T. Fujita, F. Hatori, and T. Sakurai, "Variable threshold-voltage CMOS technology," IEICE Trans. Electron., vol. E83-C, pp. 1705-1715, Nov. 2000.
81. T. Sakurai, "Low power integrated circuit technologies for high-performance: Extremely low-power mobile information terminals," in Int. Conf. Solid State Devices and Materials, 2000, pp. 3-25.
82. S. Mutoh, S. Shigematsu, Y. Gotoh, and S. Konaka, "Design method of MTCMOS power switch for low-voltage high-speed LSIs," in IEEE Asia-South Pacific Design Automation Conf., 1999, pp. 113-116.
83. K.-T. Park, T. Mizukusa, H.-S. Won, K.-M. Choi, J.-T. Kong, H. Kurino, and M. Koyanagi, "Low-power data-preserving complementary pass-transistor-based circuit for power-down circuit scheme," in Int. Conf. Solid State Devices Materials, 2001, pp. 100-101.
84. T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9 V 150 MHz 10 mW 4 mm2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in IEEE Solid-State Circuits Conf. Dig., 1996, pp. 166-167.
85. K. K. Das and R. B. Brown, "Ultra low-leakage power strategies for sub-1 V VLSI: Novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology," in Int. Conf. VLSI Design, 2003, pp. 291-296.
86. T. Hiromoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "Optimum device parameters and scal-ability of variable threshold CMOS (VTCMOS)," in Int. Conf. Solid State Devices Materials, 2000, pp. 372-373.
87. T. Douseki, J. Yamada, and H. Kyuragi, "Ultralow-power CMOS/SOI LSI design for future mobile systems," in Symp. VLSI Circuits, 2002, pp. 6-9.
88. F. Caignet, S. D. Bendhia, and E. Sicard, "The challenge of signal integrity in deep-submicrometer CMOS technology," Proc. IEEE, vol. 89, pp. 556-573, Apr. 2001.
89. N. S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, and C. Cantrell, "Benchmarks for interconnect parasitic resistance and capacitance," in IEEE Int. Symp. Quality Electronic Design, 2003, pp. 163-168.
90. S. S. Wong, P. Yue, R. Chang, S. Kim, B. Kleveland, and F. O'Mahony, "On-chip interconnect inductance-friend or foe," in IEEE Int. Symp. Quality Electronic Design, 2003, pp. 389-394.
91. P. Li and L. T. Pileggi, "NORM: Compact model order reduction of weakly nonlinear systems," in IEEE Design Automation Conf., 2003, pp. 472-477.
92. J. F. Croix and D. F. Wong, "Blade and Razor: Cell and interconnect delay analysis using current-based models," in IEEE Design Automation Conf., 2003, pp. 386-389.
93. K. Agarwal, D. Sylvester, and D. Blaauw, "An effective capacitance based driver output model for on-chip RLC interconnects," in IEEE Design Automation Conf., 2003, pp. 376-381.
94. J. Cong, "An interconnect-centric design flow for nanometer technologies," Proc. IEEE, vol. 89, pp. 505-528, Apr. 2001.
95. J. S. Yang, J. Y. Kim, J. H. Choi, M. H. Yoo, and J. T. Kong, "Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis," in IEEE Int. Symp. Quality Electronic Design, 2003, pp. 344-347.
96. L. M. Silveira and N. Vargas, "Characterizing substrate coupling in deep-submicron designs," in IEEE Des. Test. Comput., vol. 19, Mar.-Apr. 2002, pp. 4-15.
97. M. V. Heijningen, M. Badaroglu, S. Donnay, G. G. E. Gielen, and H. J. DeMan, "Substrate noise generation in complex digital systems: Efficient modeling and simulation methodology and experimental verification," IEEE J. Solid-State Circuits, vol. 37, pp. 1065-1072, Aug. 2002.
98. M. Shen, L.-R. Zheng, and H. Tenhunen, "Cost and performance analysis for mixed-signal system implementation: System-on-chip or system-on-package?," IEEE Trans. Electron. Packag. Manufact., vol. 25, pp. 262-272, Oct. 2002.
99. S. Boyd and L. Vandenberghe, "Design of robust power and ground networks," in ACM/SIGDA Int. Symp. Physical Design, 2001, pp. 60-65.
100. H.-M. Chen, L.-D. Huang, I.-M. Liu/M. Lai, and D. F. Wong, "Floor-planning with power supply noise avoidance," in IEEE Asia-South Pacific Design Automation Conf., 2003, pp. 427-430.
101. K. Wang and M. Marek-Sadowska, "On-chip power supply network optimization using multigrid-based technique." in IEEE Design Automation Conf., 2003, pp. 113-118.
102. A. H. Ajami, K. Banerjee, A. Mehrotra, and M. Pedram, "Analysis of IA-drop scaling with implications for deep submicorn P/G network designs," in IEEE Int. Symp. Quality Electronic Design, 2003, pp. 35-40.
103. J.-H. Choi, Y.-S. Hong, C.-W. Ko, Y.-G. Kim, T.-S. Kim, and J.-T. Kong, "An efficient simultaneous switching noise analysis of high density multi-layer packages and PCB's considering the power and ground planes," in 6th Int. Conf. Very Large Scale Integration and Computer-Aided Design, 1999, pp. 65-68.
104. C. Constantinescu, "Impact of deep submicron technology on dependability of VLSI circuits," in Int. Conf. on Dependable Systems and Networks, 2002, pp. 205-209.
105. C.-H. Jeon, S.-Y. Kim, H.-S. Kim, and C.-B. Rim, "The impact of NBTI and HCI on deep sub-micron PMOSFETs' lifetime," in Integrated Reliability Workshop Final Report, 2002, pp. 130-132.
106. V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," in Proc. Int. Reliability Physics Symp., 2002, pp. 248-254.
107. W. Li, Q. Li, J. S. Yuan, and J. McConkey, "Hot-carrier-induced circuit degradation for 0.18-μm CMOS technology," in Int. Symp. Quality Electronic Design, 2001, pp. 284-289.
108. J. Palau, M. Calvet, P. Dodd, F. Sexton, and P. Roche, "Contribution of device simulation to SER understanding," in Proc. Int. Reliability Physics Symp., 2003, pp. 71-75.
109. A. Haggag, W. McMahon, K. Hess, K. Cheng, J. Lee, and J. Lyding, "High-performance chip reliability from short-time-tests," in Proc. Int. Reliability Physics Symp., 2001, pp. 271-279.
110. Y. Taur, "CMOS design near the limit of scaling," IBM J. Res. Develop., vol. 46, pp. 213-222, 2002.
111. A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFET's introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, pp. 1254-1260, 2003.
112. H.-S. P. Wong, "Beyond the conventional transistor," IBM J. Res. Develop., vol. 46, pp. 133-168, Mar./May 2002.
113. J. Y. Kim, C. S. Lee, S. F. Kim, I. B. Chung, Y. M. Choi, B. J. Park, J. W. Lee, D. I. Kim, Y. S. Hwang, D. S. Hwang, H. K. Hwang, J. M. Park, D. H. Kim, N. J. Kang, M. H. Cho, M. Y. Jeong, H. J. Kim, L. N. Han, S. Y. Kim, B. Y. Nam, Y. J. Park, and K. Kim, "The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond," in Symp. Very Large Scale Integration Tech., 2003, pp. 11-12.
114. S. Lai and T. Lowrey, "OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 36.5.1-36.5.4.
115. Y.-T. Kim, K.-H. Lee, W.-Y. Jung, T.-K. Kim, Y.-K. Park, and J.-T. Kong, "Study on cell characteristics of PRAM using the phase-change simulation," in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, 2003, pp. 211-214.
116. D.-H. Kim, S.-K. Sung, K.-R. Kim, B.-H. Choi, S.-W. Hwang, D. Ahn, J.-D. Lee, and B.-G. Park, "Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic," in Int. Electron Devices Meeting Tech. Dig., 2001, pp. 151-154.
117. Y.-S. Yun, S.-W. Hwang, and D. Ahn, "Macromodeling of single-electron transistors for efficient circuit simulation," IEEE Trans. Electron Devices, vol. 46, pp. 1667-1671, Aug. 1999.
118. S.-H. Lee, D.-H. Kim, K.-R. Kim, J.-D. Lee, B.-G. Park, Y.-J. Gu, G.-Y. Yang, and J.-T. Kong, "A practical SPICE model based on the physics and characteristics of realistic single-electron transistors," IEEE Trans. Nanotechnol., vol. 1, pp. 226-232, Dec., 2002.
119. M. E. Law, "Process modeling for future technologies," IBM J. Res. Develop., vol. 46, pp. 339-346, Mar./May 2002.