A fast algorithm for minimizing the elmore delay to identified critical sinks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 7, 1997, Pages 753-759

  Borah, Manjit ^a,b   Owens, Robert M ^a,b   Irwin, Mary Jane ^a,b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; ITERATIVE METHODS;

ELMORE DELAY; ROUTING ALGORITHM; STEINER ROUTE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031177080     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.644036     Document Type: Article

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