VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 5, 2003, Pages 755-761

  Im, Hyunsik ^a,b   Inukai, Takashi ^a,c   Gomyo, Hiroyuki ^a,d   Hiramoto, Toshiro ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b Dongguk University   (South Korea)

^c TOSHIBA CORPORATION   (Japan)

^d PANASONIC CORPORATION   (Japan)

Author keywords

Analytical model; Body effect; Low power; Substrate bias; Variable threshold voltage CMOS (VTCMOS)

Indexed keywords

ELECTRIC CURRENTS; MOSFET DEVICES; POWER SUPPLY CIRCUITS; THRESHOLD VOLTAGE;

SUBSTRATE BIAS;

CMOS INTEGRATED CIRCUITS;

EID: 0142165185     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.814320     Document Type: Article

References (10)

1. T. Kuroda et al., "A 0.9V, 15-Mhz, 10-mV, 4mm-2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," IEEE J. Solid-State Circuits, vol. 31, pp. 1770-1779, Nov. 1996.
2. H. Mizuno, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda, and K. Uchiyama, "A 18 μ A standby-current 1.8V 200MHz microprocessor with self substrate-biased data retention mode," in Proc. ISSCC Tech. Dig., 1999, p. 280.
3. T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gymyo, H. Kawaguchi, and T. Sakurai, "Optimum device parameters and scalability of variable threshold complementary MOS (VTCMOS)," Jpn. J. Appl. Phys., vol. 40, pp. 2859-2865, Apr. 2001.
4. T. Hiramoto and M. Takamiya, "Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias," IEIEC Trans. Electron., vol. E83-C, pp. 161-169, Feb. 2000.
5. H. Koura, M. Takamiya, and T. Hiramoto, "Optimum conditions of body effect factor and substrate bias in Variable threshold voltage MOSFETs," Jpn. J. Appl. Phys., vol. 39, pp. 2312-2317, Apr. 2000.
6. T. Sakurai and R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans Electron Devices, vol. 38, pp. 887-894, Apr. 1991.
7. H. Im, M. Song, T. Hiramoto, and T. Sakurai, "Physical Insight into Fractional Power Dependence of Saturation Current on Gate Voltage in Advanced Short Channel MOSFETS (Alpha-Power Law Model)," in Proc. Int. Symp. Low-Power Electronics Design (ISLPED)., CA, Aug. 2002, pp. 13-18.
8. T. Inukai, H. Im, and T. Hiramoto, "The short channel effect of an uniformly doped CMOS can be calculated by solving an implicit equation for the short channel depletion width in terms of the long channel depletion width iteratively.," in Fundamentals of Modern VLSI Devices, Y. Taur and T. H. Ning, Eds. Cambridge, U.K.: Cambridge Univ. Press, 1998.
9. T. Sakurai and A. R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE J. Solid-State Circuits, vol. 26, pp. 122-133, Feb. 1991.
10. T. Inukai, T. Hiramoto, and T. Sakurai, "Variable threshold voltage CMOS (VTCMOS) in series connected circuits," in Proc. 2001 Int. Symp. Low Power Electronics Design (ISPLED'01), 2001, pp. 201-206.