Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects

IEEE Transactions on Electron Devices

Volumn 44, Issue 11, 1997, Pages 1951-1957

  Chen, Kai ^a,b   Hu, Chenming ^a,b   Fang, Peng ^a,b   Lin, Min Ren ^c   Wollesen, Donald L ^b   Associate, ^d  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC LOADS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); SEMICONDUCTOR DEVICE MODELS; VOLTAGE DISTRIBUTION MEASUREMENT;

INTERCONNECT LOADING EFFECTS;

MOSFET DEVICES;

EID: 0031275325     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.641365     Document Type: Article

References (17)

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