Closed form solution to simultaneous buffer insertion/sizing and wire sizing

ACM Transactions on Design Automation of Electronic Systems

Volumn 6, Issue 3, 2001, Pages 343-371

  Chu, C ^a   Wong, D F ^b  

^a Iowa State University   (United States)

^b University of Texas at Austin   (United States)

Author keywords

Buffer insertion; Buffer sizing; Closed form solution; Interconnect optimization; Wire sizing

Indexed keywords

EID: 23044525393     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/383251.383256     Document Type: Article

References (32)

1. ALPERT, C., AND DEVGAN, A. 1997. Wire segmenting for improved buffer insertion. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 588-593.
2. CHEN, C.-P., AND WONG, D. F. 1996. A fast algorithm for optimal wire-sizing under Elmore delay model. In Proceedings of the IEEE ISCAS, vol. 4, pp. 412-415.
3. CHEN, C.-P., AND WONG, D. F. 1997. Optimal wire-sizing function with fringing capacitance consideration. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 604-607.
4. CHEN, C.-P., CHANG, Y.-W., AND WONG, D. F. 1996a. Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 405-408.
5. CHEN, C.-P., CHEN, Y.-P., AND WONG, D. F. 1996b. Optimal wire-sizing formula under the Elmore delay model. In Proceedings of the ACM/IEEE Design Automation Conferences, pp. 487-490.
6. CHEN, C.-P., ZHOU, H., AND WONG, D. F. 1996. Optimal non-uniform wire-sizing under the Elmore delay model. In Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 38-43.
7. CHU, C. C. N., AND WONG, D. F. 1997. Closed form solution to simultaneous buffer insertion/sizing and wire sizing. In Proceedings of the International Symposium on Physical Design, pp. 192-197.
8. CHU, C. C. N., AND WONG, D. F. 1999a. A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. Computer-Aided Des. 18, 6 (June.), pp. 787-798.
9. CHU, C. C. N., AND WONG, D. F. 1999b. A polynomial time optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Computer-Aided Des. 18, 9 (Sept.), pp. 1297-1304.
10. CONG, J., AND HE, L. 1996. Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Automation of Electronic Systems. 1, 4 (Oct).
11. CONG, J., AND LEUNG, K.-S. 1993. Optimal wiresizing under the distributed Elmore delay model. In Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 634-639.
12. CONG, J., AND PAN, Z. 1998. Interconnect performance estimation models for synthesis and design planning. In Proceedings of the ACM/IEEE International Workshop on Logic Synthesis.
13. CONG, J., KOH, C.-K., AND LEUNG, K.-S. 1996. Simultaneous buffer and wire sizing for performance and power optimization. In Proceedings of the International Symposium on Low Power Electronics and Design. (Aug.), pp. 271-276.
14. DHAR, S., AND FRANKLIN, M. A. 1991. Optimum buffer circuits for driving long uniform lines. IEEE J. Solid-State Circ. 26, 1 (Jan.), pp. 32-40.
15. DUFFIN, R. J., PETERSON, E. L., AND ZENER, C. 1967. Geometric Programming - Theory and Application. J Wiley, New York.
16. ELMORE, W. C. 1948. The transient response of damped linear network with particular regard to wideband amplifiers. J. Appl. Phys. 19, pp. 55-63.
17. FISHBURN, J. P. 1997. Shaping a VLSI wire to minimize Elmore delay. In Proceedings of the European Design and Test Conference.
18. FISHBURN, J. P., AND SCHEVON, C. A. 1995. Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, 42, 12 (Dec.), pp. 1020-1022.
19. GAO, Y., AND WONG, D. F. 1997. Optimal shape function for a bidirectional wire under Elmore delay model. In Proceedings of the IEEE International Conference on Computer-Aided Design.
20. HEDENSTIERNA, N., AND JEPPSON, K. O. 1987. CMOS circuit speed and buffer optimization. IEEE Trans. Comput-Aided Des. CAD-6, 2 (Mar.), pp. 270-281.
21. JAEGER, R. C. 1975. Comments on 'An optimized output stage for MOS integrated circuits'. IEEE J. Solid-State Circ. SC-10, 3 (June.), pp. 185-186.
22. KAY, R., BUCHEUV, G., AND PILEGGI, L. 1997. EWA: Efficient Wire-Sizing Algorithm. In Proceedings of the International Symposium on Physical Design, pp. 178-185.
23. LILLIS, J., CHENG, C.-K., AND LIN, T.-T. 1995. Optimal and efficient buffer insertion and wire sizing. In Proceedings of the Custom Integrated Circuits Conference, pp. 259-262.
24. LILLIS, J., CHENG, C.-K., AND LIN, T.-T. 1996. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid-State Circ. 31, 3 (Mar.), pp. 437-447.
25. LIN, H. C., AND LINHOLM, L. W. 1975. An optimized output stage for MOS integrated circuits. IEEE J. Solid-State Circ. SC-10, 2 (Apr.), pp. 106-109.
26. MENEZES, N., BALDICK, R., AND PILEGGI, L. T. 1995. A sequential quadratic programming approach to concurrent gate and wire sizing. In Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 144-151.
27. MENEZES, N., PULLELA, S., DARTU, F., AND PILEGGI, L. T. 1994. RC interconnect syntheses-a moment fitting approach. In Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 418-425.
28. SANCHETI, P. K., AND SAPATNEKAR, S. S. 1994. Interconnect design using convex optimization. In Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 549-552.
29. Semiconductor Industry Association. 1997. The National Technology Roadmap for Semiconductors.
30. VAN GINNEKEN, L. P. P. P. 1990. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In Proceedings of the International Symposium on Circuits and Systems, pp. 865-868.
31. XUE, T., KUH, E. S., AND YU, Q. 1996. A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies. In Proceedings of the IEEE Multi-Chip Module Conference, pp. 117-121.
32. ZHOU, D., AND LIU, X. Y. 1997. Minimization of chip size and power consumption of high-speed VLSI buffers. In Proceedings of the International Symposium on Physical Design, pp. 186-191.