Concurrent logic restructuring and placement for timing closure

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 31-35

  Lou, Jinan ^a   Chen, Wei ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONSTRAINT THEORY; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; NONLINEAR PROGRAMMING; OPTIMIZATION; PERFORMANCE; POLYNOMIALS;

CONCURRENT LOGIC RESTRUCTURING; GENERALIZED GEOMETRIC PROGRAMMING; VERY DEE P SUBMICRONS;

ALGORITHMS;

EID: 0033337594     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)