Converter-free multiple-voltage scaling techniques for low-power CMOS digital design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 1, 2001, Pages 172-176

  Yeh, Yi Jong ^a   Kuo, Sy Yen ^a   Jou, Jing Yang ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

CFMV; Clustered voltage scaling; Converter free; CVS; Low power; Multiple voltage; Voltage scaling

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; POWER CONVERTERS; ROUTERS;

CONVERTER-FREE MULTIPLE-VOLTAGE SCALING TECHNIQUES;

CMOS INTEGRATED CIRCUITS;

EID: 0035063059     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.905685     Document Type: Article

References (14)

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