Supply voltage scaling for temperature insensitive CMOS circuit operation

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 3, 1998, Pages 415-417

  Bellaouar, A ^a   Fridi, A ^a   Elmasry, M I ^a   Itoh, K ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Circuits; CMOS; Digital; Temperature effects

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; NAND CIRCUITS; SEMICONDUCTOR DEVICE MODELS; THERMAL EFFECTS; VLSI CIRCUITS;

SUPPLY VOLTAGE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0032025630     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.664253     Document Type: Article

References (3)

1. R. Brodersen, A. Chandrakasan, and S. Sheng, Design techniques for portable systems, ISSCC'93 Tech. Dig., pp. 168-169, 1993.
2. M. Kakumu, Process and device technologies of CMOS devices for low-voltage operations, IEICE Trans. Electronics, vol. E76-C, pp. 672-680, May 1993.
3. S. W. Sun and P. G. Y. Tsui, Limitation of CMOS supply-voltage scaling by MOSFET threshold voltage variation, IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 947-949, Aug. 1995.