Dynamic frequency scaling with buffer insertion for mixed workloads

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 11, 2002, Pages 1284-1305

  Lu, Yung Hsiang ^a   Benini, Luca ^b   De Micheli, Giovanni ^c  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c Stanford University   (United States)

Author keywords

Frequency scaling; Multimedia; Power reduction

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; CONSTRAINT THEORY; FREQUENCIES; GRAPH THEORY; IMAGE COMPRESSION; INTERACTIVE COMPUTER SYSTEMS; MULTIMEDIA SYSTEMS; PERSONAL COMPUTERS; RESPONSE TIME (COMPUTER SYSTEMS); STANDARDS; VOLTAGE MEASUREMENT;

DATA BUFFERS; FREQUENCY ASSIGNMENT GRAPHS; FREQUENCY SCALING METHOD; GRAPH WALK ALGORITHM; MOTION PICTURE EXPERTS GROUP; POWER REDUCTION;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0036864780     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804087     Document Type: Article

References (41)

1. A. Acquaviva, L. Benini, and B. Riccó, "An adaptive algorithm for low-power streaming multimedia processing," In Design Automation Test Europe, Mar. 2001, pp. 273-279.
2. ARM Linux. Available:http://www.arm.linux.org.uk
3. R. Balakrishnan and K. Ranganathan, A Textbook of Graph Theory. New York: Springer, 2000.
4. L. Benini, A. Bogliolo, and G. D. Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans. VLSI Syst., vol. 8, pp. 299-316, June 2000.
5. J. R. Birge and F. Louveaux, Introduction to Stochastic Programming. New York: Springer, 1997.
6. J. J. Brown, D. Z. Chen, G. W. Greenwood, X. Hu, and R. W. Taylor, "Scheduling for power reduction in a real-time system," in Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1997, pp. 84-87
7. T. D. burd and R. W. Brodersen, "Design issues for dynamic voltage scaling," in Int. Symp. Low Power Electronics and Design, July 2000, pp. 9-14.
8. G. C. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. New York: Kluwer, 1997.
9. L. H. Chandrasena and M. J. Liebelt, "A rate selection algorithm for quantized undithered dynamic supply voltage scaling," in Int. Symp. Low Power Electronics and Design, July 2000, pp. 213-215.
10. D. Coppersmith, P. Doyle, P. Raghavan, and M. Snir, "Random walks on weighted graphs and applications to on-line algorithms," J. Assoc. Computing Machinery, vol. 40, no. 3, pp. 421-453, July 1993.
11. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. New York: McGraw-Hill, 1990.
12. R. Diestel, Graph Theory. New York: Springer, 1997.
13. A. Forestier and M. R. Stan, "Limits to voltage scaling from the low power perspectiv," in Symp. Integrated Circuits Systems Design, Sept. 2000, pp. 365-370.
14. K. Govil, E. Chan, and H. Wasserman, "Comparing algorithms for dynamic speed-setting of a low-power CPU," in ACM Int. Conf. Mobile Computing Networking, Nov. 1995, pp. 13-25.
15. R. L. Graham, D. E. Knuth, and O. Patashnik, Concrete Mathematics. New York: Addison-Wesley, 1989.
16. R. P. Grimaldi, Discrete and Combinatorial Mathematics, 2 ed. New York: Addison-Wesley, 1989.
17. D. Grunwald, P. Levis, K. I. Farkas, C. B. M. III, and M. Neufeld, "Policies for dynamic clock scheduling," in Symp. Operating System Design Implementation, Oct. 2000, pp. 73-86.
18. V. Gutnik and A. P. Chandrakasan, "Embedded power supply for low-power DSP," IEEE Trans. VLSI Syst., vol. 5, pp. 425-435, Dec. 1997.
19. I. Hong, M. Potkonjak, and M. B. Srivastava, "On-line scheduling of hard real-time tasks on variable voltage processor," in Int. Conf. Computer-Aided Design, Nov. 1998, pp. 653-656.
20. C. Im, H. Kim, and S. Ha, "Dynamic voltage scheduling techniques for low power multimedia applications using buffers," in Int. Symp. Low Power Electronics and Design, Aug. 2001, pp. 34-39.
21. Intel. StrongARM development kit. [Online]. Available: developer.intel.com/design/strong.
22. T. Ishihara and H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," in Int. Symp. Low Power Electronics Design, Aug. 1998, pp. 197-202.
23. P. Kall and S. W. Wallace, Stochastic Programming. New York: Wiley, 1997.
24. A. I. Kibzun and Y. S. Kan, Stochastic Programming Problems. New York: Wiley, 1996.
25. C. Krishna and Y.-H. Lee, "Voltage-clock-scaling adaptive scheduling techniques for low power in hard real-time systems," in Real-Time Technology Applications Symp., May 2000, pp. 156-165.
26. Y.-R. Lin, C.-T. Hwang, and A. C. Wu, "Scheduling techniques for variable voltage low power designs," ACM Trans. Design Automation Electron. Syst., vol. 2, no. 2, pp. 81-97, Apr. 1997.
27. J. Luo and N. Jha, "Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems," in Int. Conf. Computer-Aided Design, Nov. 2000, pp. 357-364.
28. A. Manzak and C. Chakrabarti, "Variable voltage task scheduling for minimizing energy or minimizing power," in Int. Conf. Acoustics, Speech, Signa; Processing, June 2000, pp. 3239-3242.
29. T. L. Martin and D. P. Siewiorek, "The impact of battery capacity and memory bandwidth on CPU speed-setting: A case study," in Int. Symp. Low Power Electronics Design, Aug. 1999, pp. 200-205.
30. T. Okuma, T. Ishihara, and H. Yasuura, "Real-time task scheduling for a variable voltage processor," in Int. Symp. System Synthesis, Nov. 1999, pp. 24-29.
31. T. Pering, T. burd, and R. Brodersen, "The simulation and evaluation of dynamic voltage scaling algorithms," in Int. Symp. Low Power Electronics and Design, Aug. 1998, pp. 76-81.
32. J. Pouwelse, K. Langendoen, and H. Sips, "Energy priority scheduling for variable voltage processors," in Int. Symp. Low Power Electronics and Design, Aug. 2001, pp. 28-33.
33. J. M. Rabaey and M. Pedram, Eds., Low Power Design Methodologies. New York: Kluwer, 1996.
34. S. Ross, Introduction to Stochastic Dynamic Programming. New York: Academic, 1983.
35. Y. Shin, K. Choi, and T. Sakurai, "Power optimization of real-time embedded systems on variable speed processors," in Int. Conf. Computer-Aided Design, Nov. 2000, pp. 365-368.
36. T. Šimuníc, L. Benini, A. Acquaviva, P. Glynn, and G. D. Michel, "Dynamic voltage scaling for portable systems," in Design Automation Conf., June 2001, pp. 524-529.
37. M. Weiser, B. Welch, A. Demers, and S. Shenker, "Scheduling for reduced CPU energy," in Symp. Operating Systems Design Implementation, Monterey, CA, Nov. 1994, pp. 13-23.
38. N. H. Weste and K. Eshraghian, Principles of CMOS VLSI Design. New York: Addison Wesley, 1993.
39. L. A. Wolsey, Integer Programming. New York: Wiley, 1998.
40. XScale.. [Online]. Available: http://www.intel.com/design/intelxscale/.
41. A. Zemanian, "Wandering through infinity," in IEEE Int. Symp. Circuits Systems, May 1992, pp. 1749-1750.