VLSI Circuit Performance Optimization by Geometric Programming

Annals of Operations Research

Volumn 105, Issue 1-4, 2001, Pages 37-60

  Chu, Chris ^a   Wong, D F ^b  

^a Iowa State University   (United States)

^b University of Texas at Austin   (United States)

Author keywords

Circuit performance optimization; Gate sizing; Lagrangian relaxation; Transistor sizing; Unary geometric programming; VLSI design; Wire sizing

Indexed keywords

EID: 0035567587     PISSN: 02545330     EISSN: 15729338     Source Type: Journal    
DOI: 10.1023/A:1013345330079     Document Type: Article

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