Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 9, 2000, Pages 999-1010

  Jiang, Iris Hui Ru ^a   Chang, Yao Wen ^a   Jou, Jing Yang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICROMETERS; NOISE MINIMIZATION;

ALGORITHMS; CAPACITANCE; CROSSTALK; GATES (TRANSISTOR); INTERCONNECTION NETWORKS; MICROMETERS; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034259185     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.863640     Document Type: Article

References (27)