Timing Modeling and Optimization Under the Transmission Line Model

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 1, 2004, Pages 28-41

  Chen, Tai Chen ^a   Pan, Song Ra ^b   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b University of California   (United States)

Author keywords

Buffer sizing; Delay model; Inductance; Interconnect; Performance optimization; Transmission line; Wire sizing

Indexed keywords

BUFFER AMPLIFIERS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRIC WIRE; FREQUENCIES; FUNCTIONS; LIGHT REFLECTION; MATHEMATICAL MODELS; OPTIMIZATION; SIGNAL PROCESSING;

BUFFER SIZING; DELAY MODEL; INTERCONNECT; PERFORMANCE OPTIMIZATION; WIRE SIZING;

TRANSMISSION LINE THEORY;

EID: 1342286845     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.820529     Document Type: Article

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