An analytical delay model for RLC interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 12, 1997, Pages 1507-1514

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a  

^a Los Angeles   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; EFFICIENCY; MATHEMATICAL MODELS; PARAMETER ESTIMATION; PERFORMANCE; VLSI CIRCUITS;

INTERCONNECT LINES;

INTERCONNECTION NETWORKS;

EID: 0031349694     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.664231     Document Type: Article

References (22)

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