A new method for design of robust digital circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 676-681

  Patil, Dinesh ^a   Yun, Sunghee ^a   Kim, Seung Jean ^a   Cheung, Alvin ^a   Horowitz, Mark ^a   Boyd, Stephen ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OPTIMIZATION; COMPUTATIONALLY EFFICIENT; ENVIRONMENTAL VARIATIONS; GEOMETRIC PROGRAMMING; MONTE-CARLO SIMULATIONS; PERFORMANCE VARIATIONS; POLYNOMIAL FUNCTIONS; STANDARD DEVIATION;

ENVIRONMENTAL TECHNOLOGY; HEURISTIC PROGRAMMING; INTELLIGENT SYSTEMS; PRINTED CIRCUIT DESIGN;

DESIGN;

EID: 84886702569     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.11     Document Type: Conference Paper

References (21)

1. A. Conn, I. Elfadel, W. Molzen, P. O'Brien, P. Strenski, C. Visweswariah, and C. Whan, "Gradient-based optimization of custom circuits using a static-timing formulation", Proc. Design Automation Conference (DAC), 1999, pp. 452-459.
2. S. Sapetnekar, V. Rao, P. Vaidya, and S.-M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1621-1634, November 1993.
3. M. Pelgrom, C. Duinmaijer, and A.Welbers, "Matching properties of MOS transistors", IEEE Journal of Solid State Circuits, pp. 1433-1440, October 1989.
4. S. Nassif, "Within-chip variability analysis", Proc. of IEDM, 1998, p. 283.
5. K. Chen, C. Hu, P. Fang, M. Lin, and D. Wollesen, "Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects", IEEE Transactions on Electron Devices, pp. 1951-1957, November 1997.
6. J. Rubenstein, P. Penfi eld and M. Horowitz, "Signal delay in RC tree networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 202-211, July 1983.
7. M. A. Horowitz, Timing Models for MOS circuits, Ph.D. Thesis, Stanford University, 1983.
8. K.-Y. Toh, P.-K. Ko, and R. Meyer, "An engineering model for short channel MOS devices", IEEE Journal of Solid-State Circuits, pp. 950-958, August 1988.
9. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshabvarzi and V. De, "Parameter variations and impact on circuits and architecture", Proc. Design Automation Conference (DAC), 2002, pp. 58-63.
10. M. Orshansky and A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations", Proc. Design Automation Conference (DAC), 2004, pp. 337-342.
11. A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation from static timing analysis", Proc. International Symposium on Quality Electronic Design (ISQED), 2001, pp. 437-442.
12. C. Vishweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis", Proc. Design Automation Conference (DAC), 2004, pp. 331-336.
13. X. Bai, C. Vishweswariah, P. Strenski, and D. Hathaway, "Uncertainty-aware circuit tuning", Proc. Design Automation Conference (DAC), 2002, pp. 338-342.
14. M. Hashimoto and H. Onodera, "A performance optimization method by gate sizing using statistical static timing analysis", Proc. ACM/SIGDA International Symposium on Physical Design, 2000, pp. 111-116.
15. S. Raj, S. Vrudhula, and J. Wang, "A methodology to improve timing yield in the presence of process variations", Proc. Design Automation Conference (DAC), 2004, pp. 448-453.
16. E. Jacobs and M. Berkelaar, "Gate sizing using a statistical delay model", Proc. of Design, Automation, and Test in Europe, 2000, pp. 283-291.
17. S. Knowles, "A family of adders", Proc. 15th IEEE symposium on Computer Arithmetic, 2001, pp. 177-182.
18. S. Kim, S. Boyd, S. Yun, D. Patil, and M. Horowitz, "A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit design", Technical report, Stanford University, Stanford, CA 94305, 2004. Available from www.stanford.edu/boyd/heur-san-opt.html.
19. S. Boyd, S. Kim, L. Vandenberghe, and A. Hassibi, "A tutorial on geometric programming", Technical report, Stanford University, Stanford, CA 94305, 2004. Available from www.stanford.edu/boyd/gp-tutorial.html.
20. S. Boyd, and L. Vandenberghe, Convex Optimization, Cambridge University Press, 2003.
21. MOSEK ApS, The MOSEK Optimization Tools Version 2.5. User's Manual and Reference, 2002. Available from www.mosek.com.