Design and optimization of multithreshold CMOS (MTCMOS) circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 10, 2003, Pages 1324-1342

  Anis, Mohab ^a   Areibi, Shawki ^b   Elmasry, Mohamed ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

^b UNIVERSITY OF GUELPH   (Canada)

Author keywords

Ground bounce; Leakage power; Low power; Multithreshold voltage

Indexed keywords

ADDERS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; OPTIMIZATION; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE; VLSI CIRCUITS;

BIN PACKING TECHNIQUE; DEEP SUBMICRON; GROUND BOUNCE; LEAKAGE POWER; LOW POWER; MULTITHRESHOLD CMOS CIRCUITS; SET PARTITIONING TECHNIQUE; SLEEP TRANSISTOR;

CMOS INTEGRATED CIRCUITS;

EID: 0142118150     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818127     Document Type: Article

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