Interconnect synthesis without wire tapering

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 1, 2001, Pages 90-104

  Alpert, Charles J ^a,b   Devgan, Anirudh ^a,c   Fishburn, John P ^a,d   Quay, Stephen T ^c  

^a IEEE   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM MICROELECTRONICS   (United States)

^d NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECT SYNTHESIS TECHNIQUES; WIRE TAPERING;

ALGORITHMS; BUFFER CIRCUITS; ELECTRIC WIRE; INTERCONNECTION NETWORKS; LOGIC DESIGN; OPTIMIZATION; POLYNOMIALS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035065457     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.905678     Document Type: Article

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