GP based transistor sizing for optimal design of nanoscale CMOS inverter

Proceedings of the IEEE Conference on Nanotechnology

Volumn 2, Issue , 2003, Pages 524-527

  Pattanaik, M ^a   Banerjee, S ^a   Bahinipati, B K ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b Orissa Univ of Agril and Technology   (India)

Author keywords

Accuracy; Capacitance; CMOS technology; Delay; Frequency; Inverters; Predictive models; Semiconductor device modeling; Solid modeling; SPICE

Indexed keywords

CAPACITANCE; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; GEOMETRY; INTEGRATED CIRCUIT DESIGN; MATHEMATICAL PROGRAMMING; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SPICE;

ACCURACY; CMOS TECHNOLOGY; DELAY; FREQUENCY; PREDICTIVE MODELS; SOLID MODEL;

TRANSISTORS;

EID: 29144512584     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2003.1230962     Document Type: Conference Paper

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