Simultaneous voltage scaling and gate sizing for low-power design

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 49, Issue 6, 2002, Pages 400-408

  Chen, Chunhong ^a,b   Sarrafzadeh, Majid ^a,c  

^a IEEE   (Canada)

^b UNIVERSITY OF WINDSOR   (Canada)

^c University of California   (United States)

Author keywords

Gate sizing; Low power; Simultaneous approach; Voltage scaling

Indexed keywords

GATE SIZING; LOW-POWER DESIGN; VOLTAGE SCALING;

ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SYSTEMS; LINEAR PROGRAMMING; OPTIMIZATION;

ELECTRIC POTENTIAL;

EID: 0036624471     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2002.802964     Document Type: Article

References (28)

1. S. Raje and M. Sarrafzadeh, "Variable voltage scheduling," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 9-14.
2. J. M. Chang and M. Pedram, "Energy minimization using multiple supply voltages," IEEE Trans. VLSI Syst., vol. 5, pp. 436-443, Dec. 1997.
3. K. Usami and M. Horowitz, "Cluster voltage scaling technique for low-power design," in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 3-8.
4. K. Usami et al., "Automated low power technique exploiting multiple supply voltages applied to a media processor," in Proc. Custom Integrated Circuit Conf., 1997, pp. 131-134.
5. C. Chen and M. Sarrafzadeh, "An effective algorithm for gate-level power-delay tradeoff using two voltages," in Proc. Int. Conf. Computer Design, Oct. 1999, pp. 222-227.
6. S. Raje and M. Sarrafzadeh, "Scheduling with multiple voltages," Integration, VLSI J., vol. 23, pp. 37-59, 1997.
7. K. Usami et al., "Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques," in Proc. ACM/IEEE Design Automation Conf., June 1998, pp. 483-488.
8. P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, "A gate resizing technique for high reduction in power consumption," in Proc. Int. Symp. Low-Power Electronics and Design, 1997, pp. 281-286.
9. H. R. Lin and T. Hwang, "Power reduction by gate sizing with path-oriented slack calculation," in Proc. IEEE ASP-DAC/CHDL/VLSI, June 1995, pp. 7-12.
10. D. S. Chen and M. Sarrafzadeh, "An exact algorithm for low power library-specific gate re-sizing," in Proc. ACM/IEEE Design Automation Conf., June 1996, pp. 783-788.
11. O. Coudert, "Gate sizing for constrained delay/power/area optimization," IEEE Trans. VLSI Syst., vol. 5, pp. 465-472, Dec. 1997.
12. O. Coudert, R. Haddad, and S. Manne, "New algorithms for gate sizing: A comparative study," in Proc. ACM/IEEE Design Automation Conf., June 1996, pp. 734-739.
13. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," J. Solid-State Circuits, vol. 27, pp. 473-484, Apr. 1992.
14. R. H. Mohring, Graphs and Orders: The Role of Graphs in the Theory of Ordered Sets and Its Application, I. Rival, Ed. Amsterdam, The Netherlands: Reidal, 1984, pp. 41-101.
15. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A system for sequential circuit synthesis," Univ. of California, Berkeley, UCB/ERL M92/41, 1992.
16. R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 860-874, Aug. 1989.
17. C. Chen and M. Sarrafzadeh, "Slack equalization algorithm: Precise slack distribution for low-level synthesis and optimization," in Proc. Int. Workshop on Logic Synthesis, June 1999, pp. 190-192.
18. V. Sundararajan and K. K. Parhi, "Synthesis of low power CMOS VLSI circuits using dual supply voltages," in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 72-75.
19. C. Yeh, M. Chang, S. Chang, and W. Jone, "Gate-level design exploiting dual supply voltages for power-driven applications," in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 68-71.
20. C. Chen and M. Sarrafzadeh, "Provably good algorithm for low power consumption with dual supply voltages," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 76-79.
21. M. R. Garey and D. S. Johnson, Computers and Intractability-A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
22. D. Kagaris and S. Tragoudas, "Maximum independent sets on transitive graphs and their applications in testing and CAD," in Proc. Int. Conf. Computer-Aided Design, 1997, pp. 736-740.
23. M. Igarashi et al., "A low-power design method using multiple supply voltages," in Proc. Int. Symp. Low-Power Electronics and Design, 1997, pp. 36-41.
24. S. Roy, K. Belkhale, and P. Banerjee, "An α-approximate algorithm for delay-constraint technology mapping," in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 367-372.
25. S. C. Prasad and K. Roy, "Circuit optimization for minimization of power consumption under delay constraint," in Proc. Int. Workshop on Low-Power Design, 1994, pp. 15-20.
26. C. M. Fiduccia and R. M. Mattheyses, "A linear time heuristic for improving network partitions," in Proc. ACM/IEEE Design Automation Conf., 1982, pp. 175-181.
27. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: Applications in VLSI design," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 526-529.
28. C. Chen and M. Sarrafzadeh, "Power reduction by simultaneous voltage scaling and gate sizing," in Proc. Asia South Pacific Design Automation Conf., 2000, pp. 333-338.