Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 3, 2003, Pages 346-351

  Chabini, Noureddine ^a,b   Chabini, Ismaïl ^c   Aboulhamid, El Mostapha ^d   Savaria, Yvon ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b Princeton University   (United States)

^c Massachusetts Institute of Technology   (United States)

^d UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

Acyclic design; CMOS; Cyclic design; Multiphase clocked circuits; Multiple supply voltages; Performance constrains; Power consumption; Software pipelining; Synchronous digital design

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; HEURISTIC METHODS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; SEQUENTIAL CIRCUITS;

ACYCLIC DESIGN; CYCLIC DESIGN; MULTIPHASE CLOCKED CIRCUITS; SOFTWARE PIPELINING; SYNCHRONOUS DIGITAL DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037347054     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.807894     Document Type: Article

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