Combining dual-supply, dual-threshold and transistor sizing for power reduction

Proceedings-IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 316-321

  Augsburger, Stephanie ^a   Nikolić, Borivoje ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; POWER CONTROL; THRESHOLD VOLTAGE; TRANSISTORS;

MULTIPLE SUPPLY VOLTAGES; MULTIPLE THRESHOLD VOLTAGES; POWER REDUCTION; TRANSISTOR SIZING;

DIGITAL CIRCUITS;

EID: 0036396916     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2002.1106788     Document Type: Article

References (12)

1. J. D. Meindl, "Low power Microelectronics: Retrospect and Prospect," Proceedings of the IEEE, Vol. 83, No. 4, pp.619, 1995.
2. A. Chandrakasan, S. Sheng and R. Brodersen, "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp 473-484, April 1992.
3. V. De, et al., "Techniques for Leakage Power Reduction," in Design of High-Performance Microprocessor Circuits, IEEE Press, NJ, 2001, pp46-62.
4. J. Edmondson, "Impact of Physical Technology on Architecture," in Design of High-Performance Microprocessor Circuits, IEEE Press, NJ, 2001, pp3-24.
5. T. Kuroda, "Low-Power CMOS Circuit Design by Means of Supply-Voltage and Threshold-Voltage Control," Ph.D. Dissertation, University of Tokyo, December 1998.
6. K. Usami and M. Horowitz, "Clustered Voltage Scaling for Low-Power Design," International Symposium on Low Power Design, pp 3-8, April 1995.
7. K. Usami and M. Igarashi, "Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages," Proceedings of the Asia and South Pacific Design Automation Conference 2000, pp 123-128, January 2000.
8. N. Kato et al, "Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2V Power Supply CMOS," IEICE Transactions on Electronics, vol. E83-C, no.11, pp 1747-1754, November 2000.
9. T. Yamashita et al., "A 450MHz 64b RISC Processor Using Multiple Threshold Voltage CMOS," 2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp 414-415, February 2000.
10. J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, NJ, 1996.
11. M. Hamada, Y. Ootaguro and T. Kuroda, "Utilizing Surplus Timing for Power Reduction," Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 89-92, May 2001.
12. F. Ishihara and B. Nikolic, "Level-Converting Flip-Flops for Dual-Supply Systems," to be published, 2002.